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339 contributions in the last year
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Activity overview
Contribution activity
June 2025
Created a pull request in FPGA-Research/FABulous that received 1 comment
fix:fabric_gen Add parseBelFile import
parseBelFile import was missing after #364. Testworkflow failed silently, but this should be fixed with #366.
Opened 3 other pull requests in 1 repository
FPGA-Research/FABulous
2
open
1
merged
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Add generative IOs
This contribution was made on Jun 23
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Update mid_wires.jpg
This contribution was made on Jun 4
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fix: Add cmd2 to pyproject.toml
This contribution was made on Jun 4
Reviewed 3 pull requests in 1 repository
FPGA-Research/FABulous
3 pull requests
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feat: Add force mode, improve exception handling, correct debug log and direct command input with testing
This contribution was made on Jun 13
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YosysJson Object
This contribution was made on Jun 10
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CLI testing
This contribution was made on Jun 4
Created an issue in FPGA-Research/FABulous that received 2 comments
CLI: Extend Simulation Command for VHDL
Currently, the FABulous CLI simulation command only supports Verilog. VHDL Simulation has to be started through the Makefile, which is mostly hardc…
Opened 2 other issues in 1 repository
FPGA-Research/FABulous
2
open
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Check if NVC could replace GHDL for VHDL simluation
This contribution was made on Jun 11
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Bug: Project dir gets overwritten by environment variable
This contribution was made on Jun 10