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  1. FABulous FABulous Public

    Forked from FPGA-Research/FABulous

    Fabric generator and CAD tools

    Python 1 1

  2. FABulous_demo_ram FABulous_demo_ram Public

    Verilog 1

  3. FPGAIgnite-VGA FPGAIgnite-VGA Public

    Forked from jhspuk/FPGAIgnite-VGA

    VGA team of the FPGA Ignite Hackathon

    Python

  4. open-src-cvc open-src-cvc Public

    Forked from cambridgehackers/open-src-cvc

    Mirror of tachyon-da cvc Verilog simulator

    C

  5. open_eFPGA_v2 open_eFPGA_v2 Public

    Forked from FPGA-Research/open_eFPGA_v2

    Verilog

  6. tmux-window-name tmux-window-name Public

    Forked from ofirgall/tmux-window-name

    A plugin to name your tmux windows smartly.

    Python

339 contributions in the last year

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Activity overview

Loading A graph representing EverythingElseWasAlreadyTaken's contributions from June 23, 2024 to June 24, 2025. The contributions are 70% commits, 19% pull requests, 8% code review, 3% issues. 8% Code review 3% Issues 19% Pull requests 70% Commits

Contribution activity

June 2025

Created a pull request in FPGA-Research/FABulous that received 1 comment

fix:fabric_gen Add parseBelFile import

parseBelFile import was missing after #364. Testworkflow failed silently, but this should be fixed with #366.

+1 −0 lines changed 1 comment
Opened 3 other pull requests in 1 repository
FPGA-Research/FABulous 2 open 1 merged
Reviewed 3 pull requests in 1 repository
FPGA-Research/FABulous 3 pull requests

Created an issue in FPGA-Research/FABulous that received 2 comments

CLI: Extend Simulation Command for VHDL

Currently, the FABulous CLI simulation command only supports Verilog. VHDL Simulation has to be started through the Makefile, which is mostly hardc…

2 comments
Opened 2 other issues in 1 repository
FPGA-Research/FABulous 2 open
1 contribution in private repositories Jun 4
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