CLI: Extend Simulation Command for VHDL

[EverythingElseWasAlreadyTaken]

Currently, the FABulous CLI simulation command only supports Verilog. VHDL Simulation has to be started through the Makefile, which is mostly hardcoded.
The simulation command should be extended to also work with VHDL fabrics.

The challenge is, that GHDL needs the VHDL files analyzed and elaborated in a specific order, before the simulation can be executed. This makes automating VHDL simulation for dynamic fabrics a bit harder.
We should either find a way to automate this, or as an alternative look into NVC as a replacement for GHDL, which might support automatic elaboration.

PR #214 already tried to implement some basic simulation function for the older version of the CLI.
Maybe we can reuse some things from there.

[Biswajitks1]

https://ghdl.github.io/ghdl/using/InvokingGHDL.html
If I am not wrong the simulation is a script/make with all files in the particular order. There is something mentioned about the generate make file in the docs. I think it automatically generates a make file with the order.

[EverythingElseWasAlreadyTaken]

Thanks for the hint! We'll look into that. :)