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Check if NVC could replace GHDL for VHDL simluation

enhancementNew feature or requestNew feature or request

good first issueGood for newcomersGood for newcomers

Status: Open.

#378 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Jun 11, 2025

 ·  

FABulous 2.0

CLI: Extend Simulation Command for VHDL

enhancementNew feature or requestNew feature or request

Status: Open.

Feature

#377 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Jun 11, 2025

 ·  

FABulous 2.0

Bug: Project dir gets overwritten by environment variable

bugSomething isn't workingSomething isn't working

Status: Open.

Bug

#376 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Jun 10, 2025

 ·  

FABulous 1.5

Unify BelMap feature for VHDL and Verilog

enhancementNew feature or requestNew feature or request

good first issueGood for newcomersGood for newcomers

Status: Open.

Task

#363 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on May 23, 2025

 ·  

FABulous 2.0

Decide on a versioning system

documentationImprovements or additions to documentationImprovements or additions to documentation

enhancementNew feature or requestNew feature or request

Status: Open.

Task

#362 In FPGA-Research/FABulous;

· KelvinChung2000 opened on May 22, 2025

 ·  

FABulous 1.5

Cleanup and unify Verilog and VHDL bel files

enhancementNew feature or requestNew feature or request

good first issueGood for newcomersGood for newcomers

Status: Open.

#337 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Feb 28, 2025

 ·  

FABulous 1.5

Make bit_gen an own project

enhancementNew feature or requestNew feature or request

Status: Open.

#330 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Feb 19, 2025

 ·  

FABulous 2.0

Document legacy bitstream generation

documentationImprovements or additions to documentationImprovements or additions to documentation

Status: Open.

#323 In FPGA-Research/FABulous;

· mole99 opened on Feb 12, 2025

Add CLI option to pass a list of FABulous commands directly from shell

enhancementNew feature or requestNew feature or request

Status: Open.

#319 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Feb 7, 2025

Replace VHDL bel parser with GHDL-Yosys plugin

enhancementNew feature or requestNew feature or request

good first issueGood for newcomersGood for newcomers

waitingIssue is waits for other Issue / PR / ...Issue is waits for other Issue / PR / ...

Status: Open.

Feature

#310 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Jan 30, 2025

 ·  

FABulous 2.0

Shell is entered instead of throwing an error when the script file is an existing directory

bugSomething isn't workingSomething isn't working

Status: Open.

#302 In FPGA-Research/FABulous;

· IAmMarcelJung opened on Jan 25, 2025

Special handling of first and last row of fabric

bugSomething isn't workingSomething isn't working

Status: Open.

#297 In FPGA-Research/FABulous;

· mole99 opened on Jan 24, 2025