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Support PCF for I/Os

enhancementNew feature or requestNew feature or request

Status: Open.

#287 In FPGA-Research/FABulous;

· mole99 opened on Jan 23, 2025

Use fabric name for fabric module

enhancementNew feature or requestNew feature or request

Status: Open.

#289 In FPGA-Research/FABulous;

· mole99 opened on Jan 23, 2025

Make bit_gen an own project

enhancementNew feature or requestNew feature or request

Status: Open.

#330 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Feb 19, 2025

Unify BelMap feature for VHDL and Verilog

enhancementNew feature or requestNew feature or request

good first issueGood for newcomersGood for newcomers

Status: Open.

Task

#363 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on May 23, 2025

Replace VHDL bel parser with GHDL-Yosys plugin

enhancementNew feature or requestNew feature or request

good first issueGood for newcomersGood for newcomers

waitingIssue is waits for other Issue / PR / ...Issue is waits for other Issue / PR / ...

Status: Open.

Feature

#310 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Jan 30, 2025

YosysJson Object

Status: Draft (not ready).

FPGA-Research/FABulousnumber 367

#367 In FPGA-Research/FABulous;

· KelvinChung2000 opened on May 28, 2025

CLI: Extend Simulation Command for VHDL

enhancementNew feature or requestNew feature or request

Status: Open.

Feature

#377 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Jun 11, 2025

Check if NVC could replace GHDL for VHDL simluation

enhancementNew feature or requestNew feature or request

good first issueGood for newcomersGood for newcomers

Status: Open.

#378 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Jun 11, 2025