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Decide on a versioning system

documentationImprovements or additions to documentationImprovements or additions to documentation

enhancementNew feature or requestNew feature or request

Status: Open.

Task

#362 In FPGA-Research/FABulous;

· KelvinChung2000 opened on May 22, 2025

Cleanup and unify Verilog and VHDL bel files

enhancementNew feature or requestNew feature or request

good first issueGood for newcomersGood for newcomers

Status: Open.

#337 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Feb 28, 2025

feat: Add version number and checks

waitingIssue is waits for other Issue / PR / ...Issue is waits for other Issue / PR / ...

Status: Open (in progress).

FPGA-Research/FABulousnumber 328

#328 In FPGA-Research/FABulous;

· KelvinChung2000 opened on Feb 18, 2025

feat: Replace Black with Ruff for code linting and formatting

Needs rebaseThis PR needs to be rebased before merged.This PR needs to be rebased before merged.

waitingIssue is waits for other Issue / PR / ...Issue is waits for other Issue / PR / ...

Status: Open (in progress).

FPGA-Research/FABulousnumber 335

#335 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Feb 28, 2025

chore: Rebasing development to master

waitingIssue is waits for other Issue / PR / ...Issue is waits for other Issue / PR / ...

Status: Open (in progress).

FPGA-Research/FABulousnumber 324

#324 In FPGA-Research/FABulous;

· KelvinChung2000 opened on Feb 12, 2025

Bug: Project dir gets overwritten by environment variable

bugSomething isn't workingSomething isn't working

Status: Open.

Bug

#376 In FPGA-Research/FABulous;

· EverythingElseWasAlreadyTaken opened on Jun 10, 2025