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fabric_files:template_vhdl: Fix VHDL simulation and synthesis + add Makefile.
Fix the broken VHDL simulation and VHDL user design synthesis. Replace old simulation scripts with a Makefile. Add README for `Test`. Add .gitignore in `Test`. Update testbench, user_design and top_wrapper for simulation. Remove old floorplaning information from fabric.csv Signed-off-by: Jonas K. <[email protected]>
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‎FABulous/fabric_files/FABulous_project_template_vhdl/FABulous.tcl

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load_fabric
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run_FABulous_fabric

‎FABulous/fabric_files/FABulous_project_template_vhdl/Test/.gitignore

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tmp
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build
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*.csv
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*.fasm
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*.json
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*.bit
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*.bin
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*.txt
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*.vh
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*.vhd
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*.hex
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*.cf
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*.vcd

‎FABulous/fabric_files/FABulous_project_template_vhdl/Test/Makefile

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MAX_BITBYTES=16384
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FAB_PROJ_ROOT=..
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BUILD_DIR=build
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DESIGN=sequential_16bit_en
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TESTBENCH=${DESIGN}_tb
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TOP_WRAPPER=top_wrapper
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USER_DESIGN_DIR=${FAB_PROJ_ROOT}/user_design
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USER_DESIGN_VHDL=${USER_DESIGN_DIR}/${DESIGN}.vhdl
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TOP_WRAPPER_VERILOG=${USER_DESIGN_DIR}/${TOP_WRAPPER}.v # Still needs to be verilog, since it is more like a constraint file for yosys
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FAB_TILE_FOLDER=${FAB_PROJ_ROOT}/Tile
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FAB_FABRIC_FOLDER=${FAB_PROJ_ROOT}/Fabric
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GHDL=ghdl
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GHDL_FLAGS=--std=08 -O2 --workdir=${BUILD_DIR}
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.PHONY: all run_FABulous_demo full build_test_design run_simulation mkdir_build clean
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sim: build_test_design run_simulation clean
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full_sim: run_FABulous_demo build_test_design run_simulation clean
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build_test_design: run_yosys run_nextpnr run_bitgen
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run_FABulous_demo:
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# Runs FABulous, generates the default fabric.
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FABulous ${FAB_PROJ_ROOT} -fs ${FAB_PROJ_ROOT}/FABulous.tcl
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run_yosys: mkdir_build
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yosys -m ghdl -p "ghdl ${USER_DESIGN_VHDL} -e ${DESIGN}; read_verilog ${TOP_WRAPPER_VERILOG}; synth_fabulous -top ${TOP_WRAPPER} -json ${BUILD_DIR}/${DESIGN}.json;"
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run_nextpnr: mkdir_build
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FAB_ROOT=${FAB_PROJ_ROOT} nextpnr-generic --uarch fabulous --json ${BUILD_DIR}/${DESIGN}.json -o fasm=${BUILD_DIR}/${DESIGN}.fasm
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run_bitgen: mkdir_build
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bit_gen -genBitstream ${BUILD_DIR}/${DESIGN}.fasm ${FAB_PROJ_ROOT}/.FABulous/bitStreamSpec.bin ${BUILD_DIR}/${DESIGN}.bin
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python3 makehex.py ${BUILD_DIR}/${DESIGN}.bin ${MAX_BITBYTES} ${BUILD_DIR}/${DESIGN}.hex
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mkdir_build:
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mkdir -p ${BUILD_DIR}
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run_GTKWave:
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gtkwave ${BUILD_DIR}/${DESIGN}.fst
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clean:
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rm -rf ${BUILD_DIR}
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run_simulation: mkdir_build
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ulimit -s unlimited && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_FABRIC_FOLDER}/my_lib.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/LUT4AB/LUT4AB_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/LUT4AB/LUT4AB_ConfigMem.vhdl \
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${FAB_TILE_FOLDER}/LUT4AB/LUT4c_frame_config.vhdl \
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${FAB_TILE_FOLDER}/LUT4AB/MUX8LUT_frame_config.vhdl \
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${FAB_TILE_FOLDER}/LUT4AB/LUT4AB.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/RAM_IO/RAM_IO_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/RAM_IO/RAM_IO_ConfigMem.vhdl \
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${FAB_TILE_FOLDER}/RAM_IO/InPass4_frame_config.vhdl \
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${FAB_TILE_FOLDER}/RAM_IO/OutPass4_frame_config.vhdl \
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${FAB_TILE_FOLDER}/RAM_IO/RAM_IO.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/RegFile/RegFile_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/RegFile/RegFile_ConfigMem.vhdl \
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${FAB_TILE_FOLDER}/RegFile/RegFile_32x4.vhdl \
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${FAB_TILE_FOLDER}/RegFile/RegFile.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/W_IO/W_IO_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/W_IO/W_IO_ConfigMem.vhdl \
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${FAB_TILE_FOLDER}/W_IO/IO_1_bidirectional_frame_config_pass.vhdl \
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${FAB_TILE_FOLDER}/W_IO/Config_access.vhdl \
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${FAB_TILE_FOLDER}/W_IO/W_IO.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/DSP/DSP_top/DSP_top_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/DSP/DSP_top/DSP_top_ConfigMem.vhdl \
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${FAB_TILE_FOLDER}/DSP/DSP_top/DSP_top.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/DSP/DSP_bot/DSP_bot_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/DSP/DSP_bot/DSP_bot_ConfigMem.vhdl \
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${FAB_TILE_FOLDER}/DSP/DSP_bot/MULADD.vhdl \
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${FAB_TILE_FOLDER}/DSP/DSP_bot/DSP_bot.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/DSP/DSP_top/DSP_top.vhdl \
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${FAB_TILE_FOLDER}/DSP/DSP_bot/DSP_bot.vhdl \
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${FAB_TILE_FOLDER}/DSP/DSP.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/N_term_DSP/N_term_DSP_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/N_term_DSP/N_term_DSP.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/S_term_DSP/S_term_DSP_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/S_term_DSP/S_term_DSP.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/N_term_RAM_IO/N_term_RAM_IO_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/N_term_RAM_IO/N_term_RAM_IO.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/S_term_RAM_IO/S_term_RAM_IO_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/S_term_RAM_IO/S_term_RAM_IO.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/N_term_single/N_term_single_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/N_term_single/N_term_single.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/S_term_single/S_term_single_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/S_term_single/S_term_single.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/N_term_single2/N_term_single2_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/N_term_single2/N_term_single2.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_TILE_FOLDER}/S_term_single2/S_term_single2_switch_matrix.vhdl \
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${FAB_TILE_FOLDER}/S_term_single2/S_term_single2.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_FABRIC_FOLDER}/config_UART.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_FABRIC_FOLDER}/bitbang.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_FABRIC_FOLDER}/ConfigFSM.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_FABRIC_FOLDER}/eFPGA_Config.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_FABRIC_FOLDER}/Frame_Data_Reg.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_FABRIC_FOLDER}/Frame_Select.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_FABRIC_FOLDER}/BlockRAM_1KB.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_FABRIC_FOLDER}/eFPGA.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${FAB_FABRIC_FOLDER}/eFPGA_top.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${USER_DESIGN_DIR}/${DESIGN}.vhdl && \
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${GHDL} -a ${GHDL_FLAGS} ${TESTBENCH}.vhdl && \
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${GHDL} -e ${GHDL_FLAGS} -fexplicit ${TESTBENCH} && \
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${GHDL} -r ${GHDL_FLAGS} ${TESTBENCH} --stats --ieee-asserts=disable --fst=${BUILD_DIR}/${TESTBENCH}.fst

‎FABulous/fabric_files/FABulous_project_template_vhdl/Test/README.md

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# FABulous simulation
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This assumes FABulous is installed properly and the default instructions were followed to build the default fabric.
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FABulous provides a simulation environment to test the fabric and the bitstream generated for it.
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For simple use cases, there is the `run_simulation command` in the FABulous shell.
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For more complex use cases it can be useful to create an own flow, like the following example `make` based flow.
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Please make sure to use recent versions of (Yosys)[https://github.com/YosysHQ/yosys], (nextpnr-generic)[https://github.com/YosysHQ/nextpnr] (_not_ the old FABulous nextpnr fork)
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and (ghdl)[https://github.com/ghdl/ghdl] or use the (OSS-CAD-Suite)[https://github.com/YosysHQ/oss-cad-suite-build] which provides nightly builds of the necessary dependencies.
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Also, make sure you have the `make` package installed:
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```
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$ sudo apt-get install make
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```
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Type `make build_test_design` to create the bitstream and `make run_simulation` to compare a simulation
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of the fabric running the bitstream against the design.
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Other useful make targets are:
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- `make` or `make sim` to build the bitstream, run simulation and remove all generated files afterward.
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- `make clean` to remove all generated files
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- `make build_test_design` to build the bitstream
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- `make run_simulation` to run the simulation
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- `make run_FABulous_demo` to run the default FABulous flow
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- `make run_GTKWave` to run the GTKWave waveform viewer with the generated simulation waveform
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Take a look into the Makefile to build your own flow.

‎FABulous/fabric_files/FABulous_project_template_vhdl/Test/build_test_design.sh

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‎FABulous/fabric_files/FABulous_project_template_vhdl/Test/run_simulation_vhdl.sh

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