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fabric_files:proj_template_vhdl: Update Fabric Files
Updated Fabric files in VHDL project template. These files were generated from the Fabric files from verilog project template and are based on Biswajits work: FPGA-Research#214 Signed-off-by: Jonas K. <[email protected]>
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-928
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8 files changed

+1110
-928
lines changed

‎FABulous/fabric_files/FABulous_project_template_vhdl/Fabric/BlockRAM_1KB.vhdl

Lines changed: 26 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
-- This VHDL was converted from Verilog using the
2-
-- Icarus Verilog VHDL Code Generator 11.0 (stable) ()
2+
-- Icarus Verilog VHDL Code Generator 13.0 (devel) (s20221226-518-g94d9d1951)
33

44
library ieee;
55
use ieee.std_logic_1164.all;
@@ -23,10 +23,10 @@ entity BlockRAM_1KB is
2323
C4 : in std_logic;
2424
C5 : in std_logic;
2525
clk : in std_logic;
26-
rd_addr : in std_logic_vector(7 downto 0);
27-
rd_data : out std_logic_vector(31 downto 0);
28-
wr_addr : in std_logic_vector(7 downto 0);
29-
wr_data : in std_logic_vector(31 downto 0)
26+
rd_addr : in STD_LOGIC_VECTOR(7 downto 0);
27+
rd_data : out STD_LOGIC_VECTOR(31 downto 0);
28+
wr_addr : in STD_LOGIC_VECTOR(7 downto 0);
29+
wr_data : in STD_LOGIC_VECTOR(31 downto 0)
3030
);
3131
end entity;
3232

@@ -72,6 +72,8 @@ begin
7272
rd_port_configuration <= C2 & C3;
7373
wr_addr_topbits <= wr_data(READ_ADDRESS_MSB_FROM_DATALSB + 1 downto READ_ADDRESS_MSB_FROM_DATALSB);
7474

75+
76+
7577
-- Generated from instantiation at BlockRAM_1KB.v:75
7678
memory_cell: sram_1rw1r_32_256_8_sky130
7779
port map (
@@ -101,29 +103,29 @@ begin
101103
process (wr_port_configuration, wr_data, wr_addr_topbits) is
102104
begin
103105
muxedDataIn <= "UUUUUUUUUUUUUUUUUUUUUUUUUUUUUUUU";
104-
if wr_port_configuration = X"00000000" then
106+
if wr_port_configuration = "00" then
105107
mem_wr_mask <= X"f";
106108
muxedDataIn <= wr_data;
107109
else
108-
if wr_port_configuration = X"00000001" then
109-
if wr_addr_topbits = X"00000000" then
110+
if wr_port_configuration = "01" then
111+
if wr_addr_topbits = "00" then
110112
mem_wr_mask <= X"3";
111113
muxedDataIn(0 + 15 downto 0) <= wr_data(0 + 15 downto 0);
112114
else
113115
mem_wr_mask <= X"c";
114116
muxedDataIn(16 + 15 downto 16) <= wr_data(0 + 15 downto 0);
115117
end if;
116118
else
117-
if wr_port_configuration = X"00000002" then
118-
if wr_addr_topbits = X"00000000" then
119+
if wr_port_configuration = "10" then
120+
if wr_addr_topbits = "00" then
119121
mem_wr_mask <= X"1";
120122
muxedDataIn(0 + 7 downto 0) <= wr_data(0 + 7 downto 0);
121123
else
122-
if wr_addr_topbits = X"00000001" then
124+
if wr_addr_topbits = "01" then
123125
mem_wr_mask <= X"2";
124126
muxedDataIn(8 + 7 downto 8) <= wr_data(0 + 7 downto 0);
125127
else
126-
if wr_addr_topbits = X"00000002" then
128+
if wr_addr_topbits = "10" then
127129
mem_wr_mask <= X"4";
128130
muxedDataIn(16 + 7 downto 16) <= wr_data(0 + 7 downto 0);
129131
else
@@ -141,32 +143,32 @@ begin
141143
process (clk) is
142144
begin
143145
if rising_edge(clk) then
144-
rd_dout_sel <= wr_data(READ_ADDRESS_MSB_FROM_DATALSB + 1 downto READ_ADDRESS_MSB_FROM_DATALSB);
146+
rd_dout_sel <= wr_data(24 + 1 downto 24);
145147
end if;
146148
end process;
147149

148150
-- Generated from always process in BlockRAM_1KB (BlockRAM_1KB.v:93)
149151
process (mem_dout, rd_port_configuration, rd_dout_sel) is
150152
begin
151153
rd_dout_muxed <= mem_dout;
152-
if rd_port_configuration = X"00000000" then
154+
if rd_port_configuration = "00" then
153155
rd_dout_muxed <= mem_dout;
154156
else
155-
if rd_port_configuration = X"00000001" then
156-
if (std_logic_vector'("0000000000000000000000000000000") & rd_dout_sel(0)) = X"00000000" then
157-
rd_dout_muxed(0 + 15 downto 0) <= mem_dout(0 + 15 downto 0);
157+
if rd_port_configuration = "01" then
158+
if (rd_dout_sel(0)) = '0' then
159+
rd_dout_muxed(15 downto 0) <= mem_dout(15 downto 0);
158160
else
159161
rd_dout_muxed(0 + 15 downto 0) <= mem_dout(16 + 15 downto 16);
160162
end if;
161163
else
162-
if rd_port_configuration = X"00000002" then
163-
if rd_dout_sel = X"00000000" then
164+
if rd_port_configuration = "10" then
165+
if rd_dout_sel = "00" then
164166
rd_dout_muxed(0 + 7 downto 0) <= mem_dout(0 + 7 downto 0);
165167
else
166-
if rd_dout_sel = X"00000001" then
168+
if rd_dout_sel = "01" then
167169
rd_dout_muxed(0 + 7 downto 0) <= mem_dout(8 + 7 downto 8);
168170
else
169-
if rd_dout_sel = X"00000002" then
171+
if rd_dout_sel = "10" then
170172
rd_dout_muxed(0 + 7 downto 0) <= mem_dout(16 + 7 downto 16);
171173
else
172174
rd_dout_muxed(0 + 7 downto 0) <= mem_dout(24 + 7 downto 24);
@@ -178,6 +180,7 @@ begin
178180
end if;
179181
end process;
180182

183+
181184
-- Generated from always process in BlockRAM_1KB (BlockRAM_1KB.v:116)
182185
process (clk) is
183186
begin
@@ -231,6 +234,6 @@ end entity;
231234
-- RAM_DEPTH = 256
232235
architecture from_verilog of sram_1rw1r_32_256_8_sky130 is
233236
begin
234-
dout0 <= (others => 'Z');
235-
dout1 <= (others => 'Z');
237+
dout0 <= (others => '0');
238+
dout1 <= (others => '0');
236239
end architecture;

‎FABulous/fabric_files/FABulous_project_template_vhdl/Fabric/ConfigFSM.vhdl

Lines changed: 62 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
-- This VHDL was converted from Verilog using the
2-
-- Icarus Verilog VHDL Code Generator 11.0 (stable) ()
2+
-- Icarus Verilog VHDL Code Generator 13.0 (devel) (s20221226-518-g94d9d1951)
33

44
library ieee;
55
use ieee.std_logic_1164.all;
66
use ieee.numeric_std.all;
77

8-
-- Generated from Verilog module ConfigFSM (ConfigFSM_template.v:1)
8+
-- Generated from Verilog module ConfigFSM (ConfigFSM.v:1)
99
-- FrameBitsPerRow = 32
1010
-- NumberOfRows = 16
1111
-- RowSelectWidth = 5
@@ -19,29 +19,30 @@ entity ConfigFSM is
1919
);
2020
port (
2121
CLK : in std_logic;
22+
FSM_Reset : in std_logic;
2223
FrameAddressRegister : out std_logic_vector(31 downto 0);
2324
LongFrameStrobe : out std_logic;
24-
Reset : in std_logic;
2525
RowSelect : out std_logic_vector(4 downto 0);
2626
WriteData : in std_logic_vector(31 downto 0);
27-
WriteStrobe : in std_logic
27+
WriteStrobe : in std_logic;
28+
resetn : in std_logic
2829
);
2930
end entity;
3031

31-
-- Generated from Verilog module ConfigFSM (ConfigFSM_template.v:1)
32+
-- Generated from Verilog module ConfigFSM (ConfigFSM.v:1)
3233
-- FrameBitsPerRow = 32
3334
-- NumberOfRows = 16
3435
-- RowSelectWidth = 5
3536
-- desync_flag = 20
3637
architecture from_verilog of ConfigFSM is
3738
signal FrameAddressRegister_Reg : std_logic_vector(31 downto 0);
38-
signal LongFrameStrobe_Reg : std_logic := '0';
39+
signal LongFrameStrobe_Reg : std_logic;
3940
signal RowSelect_Reg : std_logic_vector(4 downto 0);
40-
signal FrameShiftState : unsigned(4 downto 0) := "00000"; -- Declared at ConfigFSM_template.v:19
41-
signal FrameStrobe : std_logic := '0'; -- Declared at ConfigFSM_template.v:17
42-
signal oldFrameStrobe : std_logic := '0'; -- Declared at ConfigFSM_template.v:74
43-
signal old_reset : std_logic := '0'; -- Declared at ConfigFSM_template.v:23
44-
signal state : std_logic_vector(1 downto 0) := "00"; -- Declared at ConfigFSM_template.v:22
41+
signal FrameShiftState : unsigned(4 downto 0); -- Declared at ConfigFSM.v:20
42+
signal FrameStrobe : std_logic; -- Declared at ConfigFSM.v:18
43+
signal oldFrameStrobe : std_logic; -- Declared at ConfigFSM.v:83
44+
signal old_reset : std_logic; -- Declared at ConfigFSM.v:24
45+
signal state : std_logic_vector(1 downto 0); -- Declared at ConfigFSM.v:23
4546

4647
function Boolean_To_Logic(B : Boolean) return std_logic is
4748
begin
@@ -56,49 +57,57 @@ begin
5657
LongFrameStrobe <= LongFrameStrobe_Reg;
5758
RowSelect <= RowSelect_Reg;
5859

59-
-- Generated from always process in ConfigFSM (ConfigFSM_template.v:24)
60-
process (CLK) is
60+
-- Generated from always process in ConfigFSM (ConfigFSM.v:25)
61+
P_FSM: process (resetn, CLK) is
6162
begin
62-
if rising_edge(CLK) then
63-
old_reset <= Reset;
64-
FrameStrobe <= '0';
65-
if (old_reset = '0') and (Reset = '1') then
63+
if falling_edge(resetn) or rising_edge(CLK) then
64+
if (not resetn) = '1' then
65+
old_reset <= '0';
6666
state <= "00";
6767
FrameShiftState <= "00000";
68+
FrameAddressRegister_Reg <= X"00000000";
69+
FrameStrobe <= '0';
6870
else
69-
case state is
70-
when "00" =>
71-
if WriteStrobe = '1' then
72-
if WriteData = X"fab0fab1" then
73-
state <= "01";
71+
old_reset <= FSM_Reset;
72+
FrameStrobe <= '0';
73+
if (old_reset = '0') and (FSM_Reset = '1') then
74+
state <= "00";
75+
FrameShiftState <= "00000";
76+
else
77+
case state is
78+
when "00" =>
79+
if WriteStrobe = '1' then
80+
if WriteData = X"FAB0FAB1" then
81+
state <= "01";
82+
end if;
7483
end if;
75-
end if;
76-
when "01" =>
77-
if WriteStrobe = '1' then
78-
if WriteData(20) = '1' then
79-
state <= "00";
80-
else
81-
FrameAddressRegister_Reg <= WriteData;
82-
FrameShiftState <= to_unsigned(NumberOfRows, FrameShiftState'length);
83-
state <= "10";
84+
when "01" =>
85+
if WriteStrobe = '1' then
86+
if WriteData(desync_flag) = '1' then
87+
state <= "00";
88+
else
89+
FrameAddressRegister_Reg <= WriteData;
90+
FrameShiftState <= to_unsigned(NumberOfRows,FrameShiftState'length);
91+
state <= "10";
92+
end if;
8493
end if;
85-
end if;
86-
when "10" =>
87-
if WriteStrobe = '1' then
88-
FrameShiftState <= FrameShiftState - "00001";
89-
if FrameShiftState = X"00000001" then
90-
FrameStrobe <= '1';
91-
state <= "01";
94+
when "10" =>
95+
if WriteStrobe = '1' then
96+
FrameShiftState <= FrameShiftState - "00001";
97+
if Resize(FrameShiftState, 32) = X"00000001" then
98+
FrameStrobe <= '1';
99+
state <= "01";
100+
end if;
92101
end if;
93-
end if;
94-
when others =>
95-
null;
96-
end case;
102+
when others =>
103+
null;
104+
end case;
105+
end if;
97106
end if;
98107
end if;
99108
end process;
100109

101-
-- Generated from always process in ConfigFSM (ConfigFSM_template.v:66)
110+
-- Generated from always process in ConfigFSM (ConfigFSM.v:75)
102111
process (WriteStrobe, FrameShiftState) is
103112
begin
104113
if WriteStrobe = '1' then
@@ -108,12 +117,17 @@ begin
108117
end if;
109118
end process;
110119

111-
-- Generated from always process in ConfigFSM (ConfigFSM_template.v:75)
112-
process (CLK) is
120+
-- Generated from always process in ConfigFSM (ConfigFSM.v:84)
121+
P_StrobeREG: process (resetn, CLK) is
113122
begin
114-
if rising_edge(CLK) then
115-
oldFrameStrobe <= FrameStrobe;
116-
LongFrameStrobe_Reg <= Boolean_To_Logic((FrameStrobe = '1') or (oldFrameStrobe = '1'));
123+
if falling_edge(resetn) or rising_edge(CLK) then
124+
if (not resetn) = '1' then
125+
oldFrameStrobe <= '0';
126+
LongFrameStrobe_Reg <= '0';
127+
else
128+
oldFrameStrobe <= FrameStrobe;
129+
LongFrameStrobe_Reg <= Boolean_To_Logic((FrameStrobe = '1') or (oldFrameStrobe = '1'));
130+
end if;
117131
end if;
118132
end process;
119133
end architecture;

‎FABulous/fabric_files/FABulous_project_template_vhdl/Fabric/Frame_Data_Reg.vhdl

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,14 @@
11
-- This VHDL was converted from Verilog using the
2-
-- Icarus Verilog VHDL Code Generator 11.0 (stable) ()
2+
-- Icarus Verilog VHDL Code Generator 13.0 (devel) (s20221226-518-g94d9d1951)
33

44
library ieee;
55
use ieee.std_logic_1164.all;
66
use ieee.numeric_std.all;
77

8-
8+
-- Generated from Verilog module Frame_Data_Reg (Frame_Data_Reg.v:1)
9+
-- FrameBitsPerRow = 32
10+
-- Row = 1
11+
-- RowSelectWidth = 5
912
entity Frame_Data_Reg is
1013
generic (
1114
RowSelectWidth : integer := 5;
@@ -20,13 +23,16 @@ entity Frame_Data_Reg is
2023
);
2124
end entity;
2225

23-
26+
-- Generated from Verilog module Frame_Data_Reg (Frame_Data_Reg.v:1)
27+
-- FrameBitsPerRow = 32
28+
-- Row = 1
29+
-- RowSelectWidth = 5
2430
architecture from_verilog of Frame_Data_Reg is
2531
signal FrameData_O_Reg : std_logic_vector(31 downto 0);
2632
begin
2733
FrameData_O <= FrameData_O_Reg;
2834

29-
-- Generated from always process in Frame_Data_Reg (Frame_Data_Reg_template.v:10)
35+
-- Generated from always process in Frame_Data_Reg (Frame_Data_Reg.v:10)
3036
process (CLK) is
3137
begin
3238
if rising_edge(CLK) then

‎FABulous/fabric_files/FABulous_project_template_vhdl/Fabric/Frame_Select.vhdl

Lines changed: 12 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,14 @@
11
-- This VHDL was converted from Verilog using the
2-
-- Icarus Verilog VHDL Code Generator 11.0 (stable) ()
2+
-- Icarus Verilog VHDL Code Generator 13.0 (devel) (s20221226-518-g94d9d1951)
33

44
library ieee;
55
use ieee.std_logic_1164.all;
66
use ieee.numeric_std.all;
77

8-
8+
-- Generated from Verilog module Frame_Select (Frame_Select.v:1)
9+
-- Col = 18
10+
-- FrameSelectWidth = 5
11+
-- MaxFramesPerCol = 20
912
entity Frame_Select is
1013
generic (
1114
FrameSelectWidth : integer := 5;
@@ -20,19 +23,22 @@ entity Frame_Select is
2023
);
2124
end entity;
2225

23-
26+
-- Generated from Verilog module Frame_Select (Frame_Select.v:1)
27+
-- Col = 18
28+
-- FrameSelectWidth = 5
29+
-- MaxFramesPerCol = 20
2430
architecture from_verilog of Frame_Select is
25-
signal FrameStrobe_O_Reg : std_logic_vector(19 downto 0);
31+
signal FrameStrobe_O_Reg : std_logic_vector(MaxFramesPerCol-1 downto 0);
2632
begin
2733
FrameStrobe_O <= FrameStrobe_O_Reg;
2834

29-
-- Generated from always process in Frame_Select (Frame_Select_template.v:11)
35+
-- Generated from always process in Frame_Select (Frame_Select.v:11)
3036
process (FrameStrobe, FrameSelect, FrameStrobe_I) is
3137
begin
3238
if (FrameStrobe = '1') and to_integer(unsigned(FrameSelect)) = Col then
3339
FrameStrobe_O_Reg <= FrameStrobe_I;
3440
else
35-
FrameStrobe_O_Reg <= X"00000";
41+
FrameStrobe_O_Reg <= (others => '0');
3642
end if;
3743
end process;
3844
end architecture;

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