.github:workflows: Add VHDL build and test workflow

 Rename old workflow to fabric_gen_verilog.
 Add a workflow to build and simulate a VHDL fabric.

Signed-off-by: Jonas K. <[email protected]>

Author: EverythingElseWasAlreadyTaken

.github/actions/prepare_FABulous_container/action.yaml

@@ -14,8 +14,8 @@ inputs:
     description: 'Additional python packages to install'
     required: false
     default: ''
-  install_GHDL:
-    description: 'Install GHDL'
+  install_GHDL_mcode:
+    description: 'Install GHDL with mcode backend'
     required: false
     default: false
 
@@ -31,7 +31,7 @@ runs:
     - name: Install GHDL mcode nightly
       # GHDL mcode is required to test our fabric.
       # The oss-cad-suite action installs GHDL, but with the LLVM backend, which is much slower for our simulation
-      if: ${{ inputs.install_GHDL == true }}
+      if: ${{ inputs.install_GHDL_mcode == true }}
       uses: ghdl/setup-ghdl@v1
       with:
         version: nightly

.github/workflows/fabric_gen.yml

@@ -1,9 +1,10 @@
-name: Test FABulous
+name: Test fabric generation
 
 on: [push, pull_request]
 
 jobs:
   run_verilog_simulation_CLI:
+    name: Run Verilog fabric generator flow and simulation with FABulous CLI
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v4
@@ -14,6 +15,7 @@ jobs:
           FABulous demo -fs ./demo/FABulous.tcl
 
   run_verilog_simulation_makefile:
+    name: Run Verilog fabric generator flow and simulation with FABulous makefile
     runs-on: ubuntu-latest
     steps:
       - uses: actions/checkout@v4
@@ -23,3 +25,27 @@ jobs:
           FABulous -c demo
           cd demo/Test
           make FAB_sim
+
+  run_vhdl_simulation_makefile:
+    name: Run VHDL fabric generator flow and simulation with FABulous makefile
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v4
+      - uses: ./.github/actions/prepare_FABulous_container
+        # with:
+          # install_GHDL_mcode: true
+          # GH composite workflwos do not support conditional steps yet. :(
+          # https://github.com/actions/runner/blob/main/docs/adrs/0549-composite-run-steps.md
+      - name: Install GHDL mcode nightly
+        # GHDL mcode is required to test our fabric.
+        # The oss-cad-suite action installs GHDL, but with the LLVM backend, which is much slower for our simulation
+        uses: ghdl/setup-ghdl@v1
+        with:
+          version: nightly
+          backend: mcode
+          investigate: true
+      - name: Run fabric generator flow and simulation with FABulous makefile
+        run: |
+          FABulous -c demo_vhdl -w vhdl
+          cd demo_vhdl/Test
+          make full_sim

FABulous/fabric_files/FABulous_project_template_vhdl/Test/README.md

@@ -5,9 +5,13 @@ FABulous provides a simulation environment to test the fabric and the bitstream
 For simple use cases, there is the `run_simulation command` in the FABulous shell.
 For more complex use cases it can be useful to create an own flow, like the following example `make` based flow.
 
-
 Please make sure to use recent versions of (Yosys)[https://github.com/YosysHQ/yosys], (nextpnr-generic)[https://github.com/YosysHQ/nextpnr] (_not_ the old FABulous nextpnr fork)
-and (ghdl)[https://github.com/ghdl/ghdl] or use the (OSS-CAD-Suite)[https://github.com/YosysHQ/oss-cad-suite-build] which provides nightly builds of the necessary dependencies.
+and (GHDL with mcode backend)[https://github.com/ghdl/ghdl/releases] or use the (OSS-CAD-Suite)[https://github.com/YosysHQ/oss-cad-suite-build] which provides nightly builds of the necessary dependencies.
+
+> [!NOTE]
+>
+>The OSS-CAD-Suite is providing GHDL only with LLVM backend, which increases the simulation speed for FABulous projects significantly.
+>We recommend using the latest GHDL with mcode backend for the best simulation performance.
 
 Also, make sure you have the `make` package installed:
 ```

FABulous/fabric_files/FABulous_project_template_vhdl/Test/sequential_16bit_en_tb.vhdl

@@ -157,8 +157,6 @@ begin
     bitstream <= readmemh("bitstream.hex");
     wait for 100 ps;
     report "Bitstream loaded into memory array";
-    -- resetn <= '1';
-    -- wait for 100 ps;
     resetn <= '0';
     wait for 10000 ps;
     resetn <= '1';

docs/source/simulation/simulation.rst

@@ -7,7 +7,9 @@ For more complex use cases it can be useful to create an own flow, like the foll
 
 
 Please make sure to use recent versions of (Yosys)[https://github.com/YosysHQ/yosys], (nextpnr-generic)[https://github.com/YosysHQ/nextpnr] (_not_ the old FABulous nextpnr fork)
-and (iverilog)[https://github.com/steveicarus/iverilog] or use the (OSS-CAD-Suite)[https://github.com/YosysHQ/oss-cad-suite-build] which provides nightly builds of the necessary dependencies.
+and (GHDL with mcode backend)[https://github.com/ghdl/ghdl/releases] or use the (OSS-CAD-Suite)[https://github.com/YosysHQ/oss-cad-suite-build] which provides nightly builds of the necessary dependencies.
+
+.. note:: The OSS-CAD-Suite is providing GHDL only with LLVM backend, which increases the simulation speed for FABulous projects significantly. We recommend using the latest GHDL with mcode backend for the best simulation performance.
 
 Also, make sure you have the `make` package installed: