arch: riscv: decouple mtval usefulness for FP traps from QEMU target #93735
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
zephyrbot
requested review from
carlocaione,
edersondisouza,
fkokosinski,
katsuster,
kgugala,
masz-nordic,
mgielda,
npitre,
tgorochowik,
VynDragon and
ycsin
AFOliveira
force-pushed
the
afoliveira/mtval
branch
from
40dd442 to
386b9fc
Compare
Introduce CONFIG_RISCV_NO_MTVAL_ON_FP_TRAP to handle implementations where the mtval CSR does not provide useful information during floating-point illegal instruction exceptions. The RISC-V specification states that mtval is "either set to zero or written with exception-specific information" on traps. Some implementations, including QEMU, do not populate mtval with the faulting instruction value during FP-related illegal instruction exceptions, making it unusable for FP exception handling. Previously, this behavior was hardcoded for QEMU targets only, but other CPU implementations may also lack useful mtval content for FP traps. Decoupling this from CONFIG_QEMU_TARGET and allows other platforms to properly declare this limitation. The new Kconfig option defaults to enabled for QEMU targets to maintain backward compatibility. Signed-off-by: Afonso Oliveira <[email protected]>
AFOliveira
force-pushed
the
afoliveira/mtval
branch
from
386b9fc to
7e5bb89
Compare
npitre
approved these changes
Jul 25, 2025
|
VynDragon
approved these changes
Jul 25, 2025
|
Twister failure is unrelated with my PR, correct? |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Introduce CONFIG_RISCV_NO_MTVAL_ON_FP_TRAP to handle implementations where the mtval CSR does not provide useful information during floating-point illegal instruction exceptions.
The RISC-V specification states that mtval is "either set to zero or written with exception-specific information" on traps. Some implementations, including QEMU, do not populate mtval with the faulting instruction value during FP-related illegal instruction exceptions, making it unusable for FP exception handling.
Previously, this behavior was hardcoded for QEMU targets only, but other CPU implementations may also lack useful mtval content for FP traps. Decoupling this from CONFIG_QEMU_TARGET and allows other platforms to properly declare this limitation.
The new Kconfig option defaults to enabled for QEMU targets to maintain backward compatibility.