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driver: i2s: fix nxp i2s multi-lane config #93721

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@herculanodavi herculanodavi commented Jul 25, 2025

Fix the case where multiple I2S channels are used at the same time by using the fifo combine feature.

There is a problem with MCUx's definition of FIFO combine modes (at least for using it with MIMXRT1060). This is the FCOMB field for the TCR4 (transmit) register:

image

While this is the FCOMB field for the RCR4 (receive) register:

image

Although they are different, MCUx defines the same parameter type for both:

#if defined(FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE) && FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE
/*! @brief sai fifo combine mode definition */
typedef enum _sai_fifo_combine
{
    kSAI_FifoCombineDisabled = 0U,          /*!< sai fifo combine mode disabled */
    kSAI_FifoCombineModeEnabledOnWrite,     /*!< sai fifo combine mode enabled on FIFO write */
    kSAI_FifoCombineModeEnabledOnRead,      /*!< sai fifo combine mode enabled on FIFO reads */
    kSAI_FifoCombineModeEnabledOnReadWrite, /*!< sai fifo combined mode enabled on FIFO read/writes */
} sai_fifo_combine_t;
#endif

While semantically the TX fifo combine parameter should be "enabled on write", it is written as "enabled on read" so that the undelying value produces the effect we want.

Fixes #88294

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Resolves #88294

@herculanodavi herculanodavi force-pushed the fix/i2s-mcux-multi-lane branch 2 times, most recently from 2ff12da to a745b8a Compare July 25, 2025 13:35
Fix the case where multiple I2S channels are used at
the same time by using the fifo combine feature.

Signed-off-by: Davi Herculano <[email protected]>
@herculanodavi herculanodavi force-pushed the fix/i2s-mcux-multi-lane branch from a745b8a to b435011 Compare July 27, 2025 22:27
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MCUX NXP SAI not working with more than one tx/rx channel
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