arch: arm: cortex_m: scb: Consolidate SCB APIs and add backup/restore functions (2nd attempt) #93699
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mathieuchopstm
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For some reason, CI adds both CMSIS 5 and CMSIS 6 to include path in this order. Because CMSIS 5 comes first, its outdated definitions are taken and build is broken: On the other hand, |
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Keeping this open for re-introduction of #93161 when CI issues are fixed. |
mathieuchopstm
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sure just trying to figure why both cmsis path are included, doubt it's intentional, the example application does not checkout cmsis, it only has cmsis_6 in manifest so it works there |
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would be also nice to understand why CI did not catch it, has to be an interaction with something else that got merged in the meantime --- oh I see now, it only works with both cmsis packages |
More specifically, CI has both @msmttchr's PR was written with CMSIS 5 in mind so CI was all but happy 🙂 |
Sorry about this, its my fault for suggesting to use SHP and SHPR. Initially when the PR was just using SHPR, I think CI reported an error and I too ran the PR locally to see the SHPR error but I missed that it was specific from CMSIS and not CMSIS_6. |
Nah don't worry about it, it's really a CI setup shortcoming let's make sure to fix that, opened #93715 for it |
Add new API to save and restore SCB context. This is typically useful when
entering and exiting suspend-to-RAM low-power modes.
The scb_context_t and the backup/restore functions are designed to only
handle SCB registers that are:
- Mutable: Their values can be changed by software.
- Configurable: They control system behavior or features.
- Stateful: Their values represent a specific configuration that an
application might want to preserve and restore.
Registers excluded from backup/restore are:
1. CPU/feature identification registers
Motivation: These registers are fixed in hardware and read-only.
2. ICSR (Interrupt Control and State Register)
Motivation: Most bits of ICSR bits are read-only or write-only
and represent volatile system state. STTNS is the only read-write
field and could be considered part of the system state, but it is
only present on certain ARMv8-M CPUs, and Zephyr does not use it.
3. CFSR (Configurable Fault Status Register)
HFSR (HardFault Status Register)
DFSR (Debug Fault Status Register)
AFSR (Auxiliary Fault Status Register)
MMFAR (MemManage Fault Address Register)
BFAR (BusFault Address Register)
Motivation: These registers are read/write-one-to-clear and
contain only fault-related information (which is volatile).
Signed-off-by: Mathieu Choplain <[email protected]>
Co-authored-by: Michele Sardo <[email protected]>
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mathieuchopstm
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Pushed cleaned-up code from #93161 that should be OK for integration once CI uses CMSIS 6. |
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@mathieuchopstm, thanks for this PR!!! |
CMSIS 5 had a different name for the SHP/SHPR registers depending on which Cortex-M was used. This inconsistency is fixed in CMSIS 6, which is the new default for Cortex-M in Zephyr.
Remove the conditional and always use SHPR in the SCB backup/restore code.
Should fix
example-applicationbreakage as seen here https://github.com/zephyrproject-rtos/example-application/actions/runs/16510871831