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Pull requests: riscv/sail-riscv

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Pull requests list

add option to control tval update by ebreak configuration Additional configuration settings needed for the model
#1191 opened Aug 5, 2025 by chihminchao Loading…
6
Implement JSON schema validation for the configuration.
#1189 opened Aug 1, 2025 by pmundkur • Draft
3
Add support for Zvfbfwma extension extension Adds support for a RISC-V extension
#1185 opened Jul 31, 2025 by nadime15 Loading…
3
Add support for Zvfbfmin extension extension Adds support for a RISC-V extension
#1184 opened Jul 31, 2025 by nadime15 Loading…
3
Load ELFs via ELFIO and add symbols to the trace output
#1177 opened Jul 29, 2025 by Timmmm Loading…
7
riscv_sim.cpp: add SIGINT processor.
#1172 opened Jul 26, 2025 by Arielfoever Loading…
5
Add DYN (Position-Independent Executable file) support
#1171 opened Jul 26, 2025 by Arielfoever • Draft
20
Add gating for vector instructions. extension Adds support for a RISC-V extension
#1170 opened Jul 26, 2025 by wwwwwwOwO Loading…
Refactor vector extension configuration. configuration Additional configuration settings needed for the model extension Adds support for a RISC-V extension
#1163 opened Jul 24, 2025 by wwwwwwOwO Loading…
20
Validate JSON config file with schema
#1161 opened Jul 23, 2025 by Arielfoever • Draft
1
41
Add support for Zfbfmin extension extension Adds support for a RISC-V extension
#1158 opened Jul 21, 2025 by nadime15 Loading…
10
Update reset vector
#1155 opened Jul 21, 2025 by Timmmm Loading…
3
config: add template rvd.json.in to generate config
#1151 opened Jul 19, 2025 by Arielfoever Loading…
1
11
Rename xlen to mxlen in the config.
#1149 opened Jul 17, 2025 by pmundkur Loading…
4
Make architecture checks in currentlyEnabled dynamic by checking cur_architecture() instead of xlen.
#1148 opened Jul 16, 2025 by pmundkur Loading…
7
Replace rv_16_random_bits implemention with cpp std mt19937
#1131 opened Jul 8, 2025 by KotorinMinami Loading…
6
Add support for local counter-overflow interrupts
#1122 opened Jul 3, 2025 by trdthg Loading…
5
Add Remote bit bang protocol support for GDB/OpenOCD integration
#1121 opened Jul 2, 2025 by nadime15 Loading…
23
Add csr_name_map and is_CSR_defined for H_ext registers
#1110 opened Jun 30, 2025 by trdthg • Draft
6
Add a cosimulator API for lockstep simulation with another simulator.
#1102 opened Jun 25, 2025 by pmundkur • Draft
4
Move RVFI to C
#1099 opened Jun 25, 2025 by trdthg Loading…
57
Add VU and VS privilege level
#1067 opened Jun 19, 2025 by trdthg Loading…
29
Add current virtualization mode register
#1061 opened Jun 17, 2025 by trdthg Loading…
12
improve handling illegal vector destination registers in decoder
#1042 opened Jun 13, 2025 by KotorinMinami Loading…
1
Adding support for (project) fast track extension Zvkgs extension Adds support for a RISC-V extension
#1017 opened Jun 7, 2025 by nibrunieAtSi5 • Draft
3
ProTip! What’s not been updated in a month: updated:<2025-07-08.