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    312 repositories

    • nanohydra

      Public
      Python
      •
      Apache License 2.0
      •0•1•0•0•Updated Jul 28, 2025Jul 28, 2025

    • wakelet

      Public
      Standalone, tiny, and low-power infrastructure to boost the HWPE flexiblity for always-on domains.
      Tcl
      •
      Apache License 2.0
      •0•1•0•0•Updated Jul 28, 2025Jul 28, 2025

    • snitch_cluster

      Public
      An energy-efficient RISC-V floating-point compute cluster.
      C
      •
      Apache License 2.0
      •81•98•21•7•Updated Jul 28, 2025Jul 28, 2025

    • picobello

      Public
      whatever it means
      C
      •
      Other
      •6•9•7•5•Updated Jul 28, 2025Jul 28, 2025

    • ace

      Public
      SystemVerilog
      •
      Other
      •5•17•0•1•Updated Jul 28, 2025Jul 28, 2025

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •22•9•1•6•Updated Jul 27, 2025Jul 27, 2025

    • chimera

      Public
      Python
      •
      Other
      •4•17•9•4•Updated Jul 27, 2025Jul 27, 2025

    • datamover

      Public
      C
      •
      Other
      •0•1•0•1•Updated Jul 26, 2025Jul 26, 2025

    • pulp-sdk

      Public
      C
      •
      Apache License 2.0
      •77•114•17•8•Updated Jul 25, 2025Jul 25, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •71•271•13•25•Updated Jul 25, 2025Jul 25, 2025

    • obi

      Public
      OBI SystemVerilog synthesizable interconnect IPs for on-chip communication
      SystemVerilog
      •
      Other
      •5•14•1•9•Updated Jul 25, 2025Jul 25, 2025

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •176•637•32•14•Updated Jul 25, 2025Jul 25, 2025

    • hwpe-stream

      Public
      IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •20•19•3•4•Updated Jul 25, 2025Jul 25, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •813•21•0•6•Updated Jul 25, 2025Jul 25, 2025

    • MAGIA

      Public
      Large-scale 2D mesh system with dedicated GeMM, on-chip RDMA and Rendez-vous accelerators.
      SystemVerilog
      •
      Apache License 2.0
      •2•3•2•0•Updated Jul 25, 2025Jul 25, 2025

    • magia-sdk

      Public
      C
      •2•2•0•0•Updated Jul 25, 2025Jul 25, 2025

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •29•105•5•4•Updated Jul 25, 2025Jul 25, 2025

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •14•14•5•4•Updated Jul 25, 2025Jul 25, 2025

    • redundancy_cells

      Public
      SystemVerilog IPs and Modules for architectural redundancy designs.
      SystemVerilog
      •
      Other
      •9•14•0•7•Updated Jul 24, 2025Jul 24, 2025

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •35•48•7•4•Updated Jul 24, 2025Jul 24, 2025

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •62•125•2•5•Updated Jul 24, 2025Jul 24, 2025

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •304•1.3k•46•16•Updated Jul 24, 2025Jul 24, 2025

    • memory_island

      Public
      An interleaved high-throughput low-contention L2 scratchpad memory.
      SystemVerilog
      •
      Other
      •3•4•4•4•Updated Jul 24, 2025Jul 24, 2025

    • artistic

      Public
      An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
      asicrenderinggdsii
      Python
      •
      Apache License 2.0
      •2•18•1•0•Updated Jul 24, 2025Jul 24, 2025

    • bender

      Public
      A dependency management tool for hardware projects.
      Rust
      •
      Apache License 2.0
      •49•313•28•9•Updated Jul 23, 2025Jul 23, 2025

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •21•30•3•6•Updated Jul 23, 2025Jul 23, 2025

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •44•216•20•7•Updated Jul 23, 2025Jul 23, 2025

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •137•17•0•4•Updated Jul 22, 2025Jul 22, 2025

    • ManyRVData

      Public
      0•0•0•1•Updated Jul 22, 2025Jul 22, 2025

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •53•300•3•5•Updated Jul 22, 2025Jul 22, 2025