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    46 repositories

    • riscv-opcodes

      Public
      RISC-V Opcodes
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •335•0•0•0•Updated Jul 26, 2025Jul 26, 2025

    • sail-riscv

      Public
      Sail RISC-V model
      Sail
      •
      Other
      •222•0•0•0•Updated Jul 25, 2025Jul 25, 2025

    • riscv-cheri

      Public
      This repository contains the CHERI extension specification, adding hardware capabilities to RISC-V ISA to enable fine-grained memory protection and scalable compartmentalization.
      TeX
      •
      Creative Commons Attribution 4.0 International
      •37•0•0•0•Updated Jul 24, 2025Jul 24, 2025

    • riscv-iommu

      Public
      Non-ISA IOMMU specification developed by the IOMMU TG.
      C
      •
      Creative Commons Attribution 4.0 International
      •25•0•0•0•Updated Jul 24, 2025Jul 24, 2025

    • riscv-zabha

      Public
      The Zabha extension provides support for byte and halfword atomic memory operations.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •9•0•0•0•Updated Jul 24, 2025Jul 24, 2025

    • server-soc

      Public
      The repo holds the draft non-ISA Server SoC specification being developed by the Server SoC specification TG and to release intermediate releases of the specification on milestones. Further downstream this repo will be used to release specifications for public review.
      TeX
      •
      Creative Commons Attribution 4.0 International
      •11•0•0•0•Updated Jul 24, 2025Jul 24, 2025

    • riscv-sbi-doc

      Public
      Documentation for the RISC-V Supervisor Binary Interface
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •94•0•0•0•Updated Jul 16, 2025Jul 16, 2025

    • riscv-fast-interrupt

      Public
      Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •51•0•0•0•Updated Jul 14, 2025Jul 14, 2025

    • riscv-zalasr

      Public
      The ISA specification for the Zalasr extension.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •3•0•0•0•Updated Jul 13, 2025Jul 13, 2025

    • riscv-spmp

      Public
      The repo contains the SPMP architectural specification, which includes capabilities like access control of read/write/execute requests by an hart, address matching, encoding of permissions, exceptions for access violation, and support for virtualization.
      TeX
      •
      Creative Commons Attribution 4.0 International
      •14•0•0•0•Updated Jul 3, 2025Jul 3, 2025

    • riscv-trace-spec

      Public
      Working Draft of the RISC-V Processor Trace Specification
      C
      •
      Creative Commons Attribution 4.0 International
      •56•0•0•0•Updated Jun 16, 2025Jun 16, 2025

    • riscv-dot-product

      Public
      Dot-Product Extension
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •6•0•0•0•Updated Jun 9, 2025Jun 9, 2025

    • riscv-acpi-ffh

      Public
      The repo will be used to hold the draft non-ISA RISC-V ACPI Functional Fixed Hardware (FFH) specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •4•0•0•0•Updated Jun 6, 2025Jun 6, 2025

    • thead-extension-spec

      Public
      T-head vendor extension Instruction Set spec
      Makefile
      •
      Apache License 2.0
      •25•0•0•0•Updated May 30, 2025May 30, 2025

    • riscv-aia

      Public
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •22•0•0•0•Updated Mar 19, 2025Mar 19, 2025

    • riscv-zilsd

      Public
      Zilsd (Load/Store Pair for RV32) Fast-Track Extension
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •6•0•0•0•Updated Feb 21, 2025Feb 21, 2025

    • riscv-semihosting-spec

      Public
      Makefile
      •
      Creative Commons Attribution Share Alike 4.0 International
      •9•0•0•0•Updated Feb 21, 2025Feb 21, 2025

    • riscv-matrix-extension-spec

      Public
      A matrix extension proposal for AI applications under RISC-V architecture
      Makefile
      •
      Apache License 2.0
      •28•0•0•0•Updated Feb 11, 2025Feb 11, 2025

    • riscv-profiles

      Public
      RISC-V Architecture Profiles
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •43•0•0•0•Updated Feb 11, 2025Feb 11, 2025

    • riscv-j-extension

      Public
      Working Draft of the RISC-V J Extension Specification
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •20•0•0•0•Updated Jan 25, 2025Jan 25, 2025

    • riscv-control-transfer-records

      Public
      This repo contains a RISC-V ISA extension (proposal) to allow recording of control transfer history to on-chip registers, to support usages associated with profiling and debug.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •6•0•0•0•Updated Jan 7, 2025Jan 7, 2025

    • riscv-matrix-spec

      Public
      RISC-V Matrix Specification
      TeX
      •
      Creative Commons Attribution 4.0 International
      •7•0•0•0•Updated Dec 2, 2024Dec 2, 2024

    • riscv-bfloat16

      Public
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •15•0•0•0•Updated Jul 7, 2024Jul 7, 2024

    • riscv-ssqosid

      Public
      This repo will hold the specification for the proposed QoS ID extension being pursued on the fast-track process.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •5•0•0•0•Updated Jun 30, 2024Jun 30, 2024

    • riscv-asm-manual

      Public
      RISC-V Assembly Programmer's Manual
      Creative Commons Attribution 4.0 International
      •248•0•0•0•Updated May 9, 2024May 9, 2024

    • riscv-isac

      Public
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •55•0•0•0•Updated Apr 11, 2024Apr 11, 2024

    • riscv-svadu

      Public
      The Svadu extension adds support and CSR control for hardware updating of PTE A/D bits.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •2•0•0•0•Updated Mar 22, 2024Mar 22, 2024

    • riscv-zicond

      Public
      The ISA specification for the ZiCondOps extension.
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •7•0•0•0•Updated Mar 22, 2024Mar 22, 2024

    • riscv-zacas

      Public
      riscv-zacas created from docs-spec-template template
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •6•0•0•0•Updated Mar 22, 2024Mar 22, 2024

    • riscv-bitmanip

      Public
      Working draft of the proposed RISC-V Bitmanipulation extension
      Makefile
      •
      Creative Commons Attribution 4.0 International
      •66•0•0•0•Updated Mar 21, 2024Mar 21, 2024