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    155 repositories

    • BOOM-RISC-V-Processor

      Public
      Berkeley Out-of-Order RISC-V Processor
      Scala
      •
      BSD 3-Clause "New" or "Revised" License
      •462•0•0•0•Updated Apr 26, 2025Apr 26, 2025

    • Verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      C++
      •
      GNU Lesser General Public License v3.0
      •684•0•0•0•Updated Mar 22, 2025Mar 22, 2025

    • RafaelCalcada-RVX

      Public
      RISC-V microcontroller IP core developed in Verilog
      Verilog
      •
      MIT License
      •23•0•0•0•Updated Mar 22, 2025Mar 22, 2025

    • RISC-V-Instruction-Set-Architecture-Manual

      Public
      RISC-V Instruction Set Manual
      TeX
      •
      Creative Commons Attribution 4.0 International
      •726•0•0•0•Updated Mar 22, 2025Mar 22, 2025

    • Sail-RISC-V

      Public
      Sail RISC-V model
      C
      •
      Other
      •222•0•0•0•Updated Mar 21, 2025Mar 21, 2025

    • RISC-V-Architecture-Test-SIG

      Public
      Assembly
      •
      Apache License 2.0
      •232•0•0•0•Updated Mar 21, 2025Mar 21, 2025

    • ANTLR4-Grammars

      Public
      Grammars written for ANTLR v4; expectation that the grammars are free of actions.
      ANTLR
      •
      MIT License
      •3.8k•0•0•0•Updated Mar 20, 2025Mar 20, 2025

    • UCBerkeley-Chipyard

      Public
      An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
      Scala
      •
      BSD 3-Clause "New" or "Revised" License
      •730•0•0•0•Updated Mar 20, 2025Mar 20, 2025

    • ANTLR4

      Public
      ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.
      Java
      •
      BSD 3-Clause "New" or "Revised" License
      •3.4k•0•0•0•Updated Mar 19, 2025Mar 19, 2025

    • GTKWave

      Public
      GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
      C
      •
      GNU General Public License v2.0
      •135•0•0•0•Updated Mar 18, 2025Mar 18, 2025

    • LukeWren-Hazard3

      Public
      3-stage RV32IMACZb* processor with debug
      Verilog
      •
      Apache License 2.0
      •64•0•0•0•Updated Mar 16, 2025Mar 16, 2025

    • UCB-Shuttle

      Public
      A Rocket-based RISC-V superscalar in-order core
      Scala
      •5•0•0•0•Updated Mar 15, 2025Mar 15, 2025

    • StephanNolting-NEORV32-Setups

      Public
      📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
      VHDL
      •
      BSD 3-Clause "New" or "Revised" License
      •27•0•0•0•Updated Mar 15, 2025Mar 15, 2025

    • Rocket-Chip-Generator

      Public
      Scala
      •
      Other
      •1.2k•0•0•0•Updated Mar 14, 2025Mar 14, 2025

    • VexiiRiscv

      Public
      Like VexRiscV, but, Harder, Better, Faster, Stronger
      Scala
      •
      MIT License
      •29•0•0•0•Updated Mar 14, 2025Mar 14, 2025

    • KuzniaRdzeni-CoreBlocks

      Public
      RISC-V out-of-order core for education and research purposes
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •19•0•0•0•Updated Mar 14, 2025Mar 14, 2025

    • NVC

      Public
      VHDL compiler and simulator
      C
      •
      GNU General Public License v3.0
      •92•0•0•0•Updated Mar 13, 2025Mar 13, 2025

    • OpenHWGroup-CORE-V-Verif

      Public
      Functional verification project for the CORE-V family of RISC-V cores.
      Assembly
      •
      Other
      •251•0•0•0•Updated Mar 13, 2025Mar 13, 2025

    • BespokeSiliconGroup-BaseJump-STL

      Public
      BaseJump STL: A Standard Template Library for SystemVerilog
      SystemVerilog
      •
      Other
      •107•0•0•0•Updated Mar 12, 2025Mar 12, 2025

    • Wildcat

      Public
      An implementation of RISC-V
      Scala
      •
      BSD 2-Clause "Simplified" License
      •8•0•0•0•Updated Mar 12, 2025Mar 12, 2025

    • Cheshire

      Public
      A Minimal Linux-Capable 64-Bit RISC-V SoC Built Around CVA6
      Verilog
      •
      Other
      •71•0•0•0•Updated Mar 11, 2025Mar 11, 2025

    • NaxRiscv

      Public
      Scala
      •
      MIT License
      •46•0•0•0•Updated Mar 10, 2025Mar 10, 2025

    • StephanNolting-NEORV32-Verilog

      Public template
      ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
      VHDL
      •
      BSD 3-Clause "New" or "Revised" License
      •17•0•0•0•Updated Mar 10, 2025Mar 10, 2025

    • PrincetonUniversity-OpenPiton

      Public
      The OpenPiton Platform
      Assembly
      •243•0•0•0•Updated Mar 9, 2025Mar 9, 2025

    • Proteus

      Public
      The SpinalHDL design of the Proteus core, an extensible RISC-V core.
      Scala
      •
      MIT License
      •11•0•0•0•Updated Mar 8, 2025Mar 8, 2025

    • Spike-RISC-V-ISA-Simulator

      Public
      Spike, a RISC-V ISA Simulator
      C
      •
      Other
      •953•0•0•0•Updated Mar 6, 2025Mar 6, 2025

    • StephanNolting-NEORV32

      Public
      32-Bit RISC-V Soft-Core CPU
      VHDL
      •
      BSD 3-Clause "New" or "Revised" License
      •272•0•0•0•Updated Mar 6, 2025Mar 6, 2025

    • OpenHWGroup-CORE-V-CVA6

      Public
      Application Class 6-Stage RISC-V CPU Capable of Booting Linux
      Assembly
      •
      Other
      •813•0•0•0•Updated Mar 6, 2025Mar 6, 2025

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •44•0•0•0•Updated Mar 6, 2025Mar 6, 2025

    • VexRiscv

      Public
      An FPGA Friendly 32-Bit RISC-V CPU Implementation
      Assembly
      •
      MIT License
      •461•0•0•0•Updated Mar 6, 2025Mar 6, 2025