v2.1.1

• Added global register offset for the SDE IP.
• Added CL_SDE software exmaple for a user allocated DMA buffer.
• Documentation to assist F2 customers with releasing AFIs and AMIs on the AWS Marketplace.
• Documentation to assist in creating a virtual desktop based on the FPGA Developer AMI running graphics-intensive applications remotely on Amazon EC2 instances.
• Fixed the BW calculation and tolerance calculation in the test_hbm_perf_random in the cl_mem_perf.

v2.1.0

Support for Vivado and Vitis 2024.2 tools.
Releasing New Developer AMI for 2024.2 tools.
Updating the asynchronous fpga_mgmt_examples to poll each FPGA once before moving to the next.

v2.0.7

Documentation updates to improve ReadTheDocs navigation and inline snippets.
XSIM template script update to extend the waveform dump time.
Added section with instructions for assigning custom PCIe IDs to HDK README.
Added supplementary XDMA driver installation guide
Updated ERRATA with fix for XSIM when simulating HBM.
Revised the Vitis README with updated code snippets, more detail about the XRT setup, and a new guided example of the Hardware Emulation workflow.
Fixed HDK DCP Tarball path issue described in #706.

v2.0.6

Releasing CL_SDE software examples to demonstrate how to use the Streaming Data Engine (SDE) DMA on small shell.
Fixing the virtual ethernet PacketGen Dual Instance Loopback example to forward packets back to the PacketGen instance.
Fixing DDR backdoor access in simulation.

v2.0.5

• Releasing instructions for using the Vivado GUI.
• Updating virtual_ethernet_install.py to no longer require sudo when run.
• Updating f2_mgmt_example, load_multiple_fpga.c, to load AFIs in parallel.
• Updated ReadTheDocs theme.
• Added the "F2 Software Performance Optimization Guide" with techniques for f2.48xlarge instances

v2.0.4

Release of f2.6xlarge instance size.

v2.0.1

Updates to HDK, SDK, and Vitis documentation. Added check for XRT install to enable Vitis hardware emulation. XRT install can now be performed automatically by running a command presented during vitis_setup.sh.

Second-Generation FPGA-Powered Amazon EC2 instances (F2)

Amazon EC2 F2 instance General Availability
F2 Instances offer customizable hardware acceleration with field programmable gate arrays (FPGAs). F2 instances are powered by up to 8 AMD Virtex UltraScale+ HBM VU47P FPGAs and are the first FPGA-based instances to feature 16GB of high-bandwidth memory. They feature a 3rd generation AMD EPYC (Milan) processor with 3x processor cores (192 vCPU), 4x networking bandwidth (100 Gbps), 2x system memory (2 TiB), and 2x NVMe SSD (7.6 TiB), compared to F1 instances.

https://aws.amazon.com/blogs/aws/now-available-second-generation-fpga-powered-amazon-ec2-instances-f2/
https://aws.amazon.com/ec2/instance-types/f2/

Migration between F1 and U200 in vivado flow is now supported

This release includes updates to the documentation and references for migration between F1 and U200 in vivado flow. The migration between F1 and U200 is now fully supported. Please refer to the FPGA developer kit v1.4.24 for support.

Release v1.4.23

FPGA developer kit now supports Xilinx Vitis/Vivado 2021.2

We recommend developers upgrade to 2021.2 to benefit from the new features, bug fixes, and optimizations. To upgrade your developer kit, make sure you use the FPGA Developer AMI v1.12.0 and simply update to the latest FPGA developer kit v1.4.23.

New features

• FPGA developer kit now supports Xilinx Vivado/Vitis 2021.2
• Updated the Vitis F1 Platform to fix an issue that could cause hangs

Note:
Currently cl_uram_example fails with 2021.2 release and we are investigating the cause of failure