update versioning and fix test

Author: KelvinChung2000

pyproject.toml

@@ -1,6 +1,6 @@
 [project]
 name = "hdlgen"
-version = "0.0.1.dev1"
+dynamic = ["version"]
 description = "An intuitive Python based HDL code generator for Verilog/SystemVerilog and VHDL."
 readme = "README.md"
 authors = [
@@ -10,9 +10,12 @@ requires-python = ">=3.12"
 dependencies = []
 
 [build-system]
-requires = ["hatchling"]
+requires = ["hatchling", "hatch-vcs"]
 build-backend = "hatchling.build"
 
+[tool.hatch.version]
+source = "vcs"
+
 [tool.hatch.build.targets.wheel]
 packages = ["src/hdlgen"]
 

tests/expected/golden_1.v

@@ -9,7 +9,7 @@ module test_module #(
 
 assign output1 = input1;
 localparam const1 = 32'd42;
-reg [7:0] signal1;
+wire [7:0] signal1;
 test #(
     .p(param1)
 ) init (