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1 parent 3ef4f89 commit 68709eeCopy full SHA for 68709ee
.github/workflows/CI.yaml
@@ -23,7 +23,7 @@ jobs:
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- name: ruff format and lint
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uses: astral-sh/ruff-action@v3
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with:
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- args: "format --check --diff -- --fix"
+ args: "format --check --diff"
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- name: Install project
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run: uv sync --all-extras --dev
pyproject.toml
@@ -1,6 +1,6 @@
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[project]
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name = "hdlgen"
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-version = "0.0.1"
+version = "0.0.1.dev1"
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description = "An intuitive Python based HDL code generator for Verilog/SystemVerilog and VHDL."
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readme = "README.md"
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authors = [
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