Dev -> Main update TO_July2025 #586
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Signed-off-by: KrzysztofHerman <[email protected]>
Signed-off-by: KrzysztofHerman <[email protected]>
Signed-off-by: KrzysztofHerman <[email protected]>
Signed-off-by: KrzysztofHerman <[email protected]>
Signed-off-by: KrzysztofHerman <[email protected]>
Signed-off-by: KrzysztofHerman <[email protected]>
…ases changed to use it. Helper procedures added to xschemrc
Annotation of key FET parameters
%d isn't appropriate here since it picks up the 0 from the rule which is meaningless so replace with actual value from the rule. Signed-off-by: Sylvain Munaut <[email protected]>
This was removed from layout rules as of v0.2 Signed-off-by: Sylvain Munaut <[email protected]>
…pport lvs Signed-off-by: KrzysztofHerman <[email protected]>
Signed-off-by: Alexey Balashov <[email protected]>
… updated in Liberty. Designs require re-synthesys of layout! Signed-off-by: Alexey Balashov <[email protected]>
Signed-off-by: Alexey Balashov <[email protected]>
Signed-off-by: Alexey Balashov <[email protected]>
…e fixed Signed-off-by: Alexey Balashov <[email protected]>
…. replace previous two pull requests Signed-off-by: Alexey Balashov <[email protected]>
Signed-off-by: KrzysztofHerman <[email protected]>
HBT's symbol update fo xschem
Fixes #339 for real this time Signed-off-by: Sylvain Munaut <[email protected]>
Signed-off-by: KrzysztofHerman <[email protected]>
Signed-off-by: Alexey Balashov <[email protected]>
…0, fix typo in sg13g2_io_notracks.lef Signed-off-by: Alexey Balashov <[email protected]>
…IGN to 0 0 Signed-off-by: Alexey Balashov <[email protected]>
…ptional
Latch-up rules are now disabled by default and needs to be enabled via
a KLayout parameter.
Example:
klayout-s -zz -s latchup_violation.gds -rd latchUpRules=true \
-r $PDK_ROOT/ihp-sg13g2/libs.tech/klayout/tech/drc/sg13g2_maximal.lydrc
Signed-off-by: Daniel Schultz <[email protected]>
Make Latch-up rules optional
Signed-off-by: Sergei Andreev <[email protected]>
Update pypreprocessor submodule
Signed-off-by: FaragElsayed2 <[email protected]>
SRAM 64x32
Signed-off-by: Alexey Balashov <[email protected]>
Stdcell Update 2. Hot Fix 2.
Signed-off-by: KrzysztofHerman <[email protected]>
Stdcell wrong format fix
….save file; fixed create .save file bug; updated examples with new launcher Signed-off-by: Patrick Fath <[email protected]>
Signed-off-by: Patrick Fath <[email protected]>
Signed-off-by: Patrick Fath <[email protected]>
Signed-off-by: Dietmar Warning <[email protected]>
complete 3rd node for resistor mismatch models
…e netlist: port order issue is fixed. LEF and Liberty are updeted for those three cells Signed-off-by: Alexey Balashov <[email protected]>
resistors. Also a reference to this library was added in ngspice .spiceinit config file. Signed-off-by: KrzysztofHerman <[email protected]>
Symbol for S-Varicap slightly modified. Signed-off-by: KrzysztofHerman <[email protected]>
Signed-off-by: Alexey Balashov <[email protected]>
Adding some updates for LVS run setup and actions
Add parallelisation implementations and examples for parameter sweeps and Monte-Carlo simulations
Modifications in IO spice netlist in order to support 3 terminal resistor model
Update KLayout DRC scripts
Stdcell Update 2. Hot Fix 3.
…accommodate larger cell sizes Signed-off-by: Sergei Andreev <[email protected]>
Signed-off-by: KrzysztofHerman <[email protected]>
Xschem DRC checks added for S-Varicap device.
Signed-off-by: Patrick Fath <[email protected]>
added missing PolyRes layer to `rsil` and `rppd` QA cells
Updated xschem example files which use .save files;
KrzysztofHerman
approved these changes
Jul 9, 2025
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