fix: addBelsToPrim does not trim bel prefixes, remove local import and make it available for VHDL fabrics

Signed-off-by: Jonas K. <[email protected]>

Author: EverythingElseWasAlreadyTaken

FABulous/fabric_generator/gen_fabric/fabric_automation.py

@@ -414,9 +414,10 @@ def addBelsToPrim(
             # check if its first port, to not set a comma before
             first = True
 
-            shared_ports = [p for p, _ in bel.sharedPort]
-
-            # external ports contain the bel prefix, but this is not needed in the prims file
+            # ports contain the bel prefix, but this is not needed in the prims file
+            inputs = [p.removeprefix(bel.prefix) for p in bel.inputs]
+            outputs = [p.removeprefix(bel.prefix) for p in bel.outputs]
+            shared_ports = [p.removeprefix(bel.prefix) for p, _ in bel.sharedPort]
             external_inputs: list[str] = []
             external_outputs: list[str] = []
             for external_port in bel.externalInput:
@@ -466,16 +467,17 @@ def addBelsToPrim(
 
                         modline += f"    {direction} {port}"
             else:  # No vector support
-                ports = bel.inputs + bel.outputs + external_ports + shared_ports
+                ports = inputs + outputs + external_ports + shared_ports
 
+                # we iterate through all ports to make the handling of the commas easier
                 for port in ports:
                     if not first:
                         modline += ",\n"
                     else:
                         first = False
-                    if port in bel.inputs:
+                    if port in inputs:
                         modline += f"    input {port}"
-                    if port in bel.outputs:
+                    if port in outputs:
                         modline += f"    output {port}"
                     if port in external_ports:
                         modline += "    (* iopad_external_pin *)\n"

FABulous/fabric_generator/parser/parse_csv.py

@@ -17,6 +17,7 @@
 from FABulous.fabric_definition.Gen_IO import Gen_IO
 from FABulous.fabric_definition.SuperTile import SuperTile
 from FABulous.fabric_definition.Tile import Tile
+from FABulous.fabric_generator.gen_fabric.fabric_automation import addBelsToPrim
 from FABulous.fabric_generator.parser.parse_hdl import parseBelFile
 from FABulous.fabric_generator.parser.parse_switchmatrix import (
     parseList,
@@ -140,19 +141,16 @@ def parseTilesCSV(fileName: Path) -> tuple[list[Tile], list[tuple[str, str]]]:
                     bels.append(parseBelFile(belFilePath, bel_prefix, "vhdl"))
                 elif temp[1].endswith(".v") or temp[1].endswith(".sv"):
                     bels.append(parseBelFile(belFilePath, bel_prefix, "verilog"))
-                    if "ADD_AS_CUSTOM_PRIM" in temp[4:]:
-                        # local import to avoid circular import
-                        from FABulous.fabric_generator.gen_fabric.fabric_automation import (
-                            addBelsToPrim,
-                        )
-
-                        primsFile = proj_dir.joinpath("user_design/custom_prims.v")
-                        logger.info(f"Adding bels to custom prims file: {primsFile}")
-                        addBelsToPrim(primsFile, [bels[-1]])
                 else:
                     raise InvalidFileType(
                         f"File {belFilePath} is not a .vhdl or .v file. Please check the BEL file."
                     )
+
+                if "ADD_AS_CUSTOM_PRIM" in temp[3:]:
+                    primsFile = proj_dir.joinpath("user_design/custom_prims.v")
+                    logger.info(f"Adding bels to custom prims file: {primsFile}")
+                    addBelsToPrim(primsFile, [bels[-1]])
+
             elif temp[0] == "GEN_IO":
                 configBit = 0
                 configAccess = False