nRF53 disrespects LFXO disabled configuration to use P0.00/P0.01 as GPIO

[ivynya]

Describe the bug

I am working with an nRF5340DK, with nRF Connect SDK v3.0.0-3bfc46578e42 and Zephyr v4.0.99-a0e545cb437a.

I wish to use P0.00/P0.01 (XL1, XL2) as GPIO instead of for the low-frequency oscillator. I did the necessary board rework to make this electrically possible, and in my device tree, I have lfxo disabled as such:

&lfxo {
    status = "disabled";
};

In my kconfig, I have this option set as well:

CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC=y

However, when I build and run my application and try to read the values I do not get correct values (as validated with a external DMM). I have also tried the deprecated method of setting CONFIG_SOC_ENABLE_LFXO=n in my proj.conf which similarly does nothing.

I am relatively confident this occurs in soc/nordic/nrf53/soc.c lines 56-72 where LFXO_CAP is always set, regardless of if LFXO is explicitly disabled by the configuration. The pins XL1, XL2 being assigned depend on LFXO_CAP and get assigned at lines 506-507 to peripheral instead of the app core - and to my understanding, rendering them inaccessible as GPIO.

I have a small proposed fix/PR for this issue: #92664

I could not determine if this is a regression or not via git history, but it seems like the now-deprecated method used to work at some point.

Regression

• This is a regression.

Steps to reproduce

For an nRF5340DK:

1. Cut SB1 and SB2
2. Solder SB3 and SB4
3. Compile a minimal app using pin 0.00 or 0.01 and attempt to read when the pin is pulled to a logical high
4. Observe that the value read is zero.

Relevant log output

Impact

Functional Limitation – Some features not working as expected, but system usable.

Environment

• macOS 15.5
• nRF Connect SDK v3.0.0-3bfc46578e42
• Zephyr v4.0.99-a0e545cb437a

Additional Context

No response

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