soc: nxp: imx95: setup m7mix and wakeupmix power on in suspend mode

wakeupmix keep power on state is essential for system
suspend mode, because of console uart locate in it.

temporarily set the M7 mix to power on,
further optimization will be carried out later

Signed-off-by: Yongxu Wang <[email protected]>

Author: yongxu-wang15

soc/nxp/imx/imx9/imx95/m7/soc.c

@@ -88,10 +88,41 @@ static int soc_init(void)
 	return ret;
 }
 
+void pm_state_before(void)
+{
+	struct scmi_cpu_pd_lpm_config cpu_pd_lpm_cfg;
+
+	/*
+	 * 1. Set M7 mix as power on state in suspend mode
+	 * 2. Keep wakeupmix power on whatever low power mode, as lpuart3(console) in there.
+	 * To do: in order to reduce power consumption, the M7 core in the i.MX95
+	 * should be powered down during suspend.
+	 * However, after being woken up by a wakeup source, the M7 CPU will restart
+	 * execution from the vector table address, which is not the desired behavior.
+	 * Instead, the vector value should be set to the address where the CPU
+	 * was before entering suspend, and the CPU state should be restored to
+	 * what it was prior to suspend.
+	 */
+
+	cpu_pd_lpm_cfg.cpu_id = CPU_IDX_M7P;
+	cpu_pd_lpm_cfg.num_cfg = 2;
+	cpu_pd_lpm_cfg.cfgs[0].domainId = PWR_MIX_SLICE_IDX_M7;
+	cpu_pd_lpm_cfg.cfgs[0].lpmSetting = SCMI_CPU_LPM_SETTING_ON_ALWAYS;
+	cpu_pd_lpm_cfg.cfgs[0].retMask = 1U << PWR_MEM_SLICE_IDX_M7;
+	cpu_pd_lpm_cfg.cfgs[1].domainId = PWR_MIX_SLICE_IDX_WAKEUP;
+	cpu_pd_lpm_cfg.cfgs[1].lpmSetting = SCMI_CPU_LPM_SETTING_ON_ALWAYS;
+	cpu_pd_lpm_cfg.cfgs[1].retMask = 0;
+
+	scmi_cpu_pd_lpm_set(&cpu_pd_lpm_cfg);
+}
+
+
 void pm_state_set(enum pm_state state, uint8_t substate_id)
 {
 	struct scmi_cpu_sleep_mode_config cpu_cfg = {0};
 
+	pm_state_before();
+
 	/* iMX95 M7 core is based on ARMv7-M architecture. For this architecture,
 	 * the current implementation of arch_irq_lock of zephyr is based on BASEPRI,
 	 * which will only retain abnormal interrupts such as NMI,

soc/nxp/imx/imx9/imx95/scmi_cpu_soc.h

@@ -23,4 +23,88 @@
 #define CPU_SLEEP_MODE_STOP     2U
 #define CPU_SLEEP_MODE_SUSPEND  3U
 
+/*!
+ * @name SCMI CPU LPM settings
+ */
+#define SCMI_CPU_LPM_SETTING_ON_NEVER          0U
+#define SCMI_CPU_LPM_SETTING_ON_RUN            1U
+#define SCMI_CPU_LPM_SETTING_ON_RUN_WAIT       2U
+#define SCMI_CPU_LPM_SETTING_ON_RUN_WAIT_STOP  3U
+#define SCMI_CPU_LPM_SETTING_ON_ALWAYS         4U
+
+/* iMX95 max scmi pd configs cpu number */
+#define SCMI_CPU_MAX_PDCONFIGS_T	7U
+
+#define CPU_PER_LPI_IDX_GPIO1           0U
+#define CPU_PER_LPI_IDX_GPIO2           1U
+#define CPU_PER_LPI_IDX_GPIO3           2U
+#define CPU_PER_LPI_IDX_GPIO4           3U
+#define CPU_PER_LPI_IDX_GPIO5           4U
+#define CPU_PER_LPI_IDX_CAN1            5U
+#define CPU_PER_LPI_IDX_CAN2            6U
+#define CPU_PER_LPI_IDX_CAN3            7U
+#define CPU_PER_LPI_IDX_CAN4            8U
+#define CPU_PER_LPI_IDX_CAN5            9U
+#define CPU_PER_LPI_IDX_LPUART1         10U
+#define CPU_PER_LPI_IDX_LPUART2         11U
+#define CPU_PER_LPI_IDX_LPUART3         12U
+#define CPU_PER_LPI_IDX_LPUART4         13U
+#define CPU_PER_LPI_IDX_LPUART5         14U
+#define CPU_PER_LPI_IDX_LPUART6         15U
+#define CPU_PER_LPI_IDX_LPUART7         16U
+#define CPU_PER_LPI_IDX_LPUART8         17U
+#define CPU_PER_LPI_IDX_WDOG3           18U
+#define CPU_PER_LPI_IDX_WDOG4           19U
+#define CPU_PER_LPI_IDX_WDOG5           20U
+
+
+/* MIX definitions */
+#define PWR_NUM_MIX_SLICE               23U
+
+#define PWR_MIX_SLICE_IDX_ANA           0U
+#define PWR_MIX_SLICE_IDX_AON           1U
+#define PWR_MIX_SLICE_IDX_BBSM          2U
+#define PWR_MIX_SLICE_IDX_CAMERA        3U
+#define PWR_MIX_SLICE_IDX_CCMSRCGPC     4U
+#define PWR_MIX_SLICE_IDX_A55C0         5U
+#define PWR_MIX_SLICE_IDX_A55C1         6U
+#define PWR_MIX_SLICE_IDX_A55C2         7U
+#define PWR_MIX_SLICE_IDX_A55C3         8U
+#define PWR_MIX_SLICE_IDX_A55C4         9U
+#define PWR_MIX_SLICE_IDX_A55C5         10U
+#define PWR_MIX_SLICE_IDX_A55P          11U
+#define PWR_MIX_SLICE_IDX_DDR           12U
+#define PWR_MIX_SLICE_IDX_DISPLAY       13U
+#define PWR_MIX_SLICE_IDX_GPU           14U
+#define PWR_MIX_SLICE_IDX_HSIO_TOP      15U
+#define PWR_MIX_SLICE_IDX_HSIO_WAON     16U
+#define PWR_MIX_SLICE_IDX_M7            17U
+#define PWR_MIX_SLICE_IDX_NETC          18U
+#define PWR_MIX_SLICE_IDX_NOC           19U
+#define PWR_MIX_SLICE_IDX_NPU           20U
+#define PWR_MIX_SLICE_IDX_VPU           21U
+#define PWR_MIX_SLICE_IDX_WAKEUP        22U
+
+#define PWR_MEM_SLICE_IDX_AON           0U
+#define PWR_MEM_SLICE_IDX_CAMERA        1U
+#define PWR_MEM_SLICE_IDX_A55C0         2U
+#define PWR_MEM_SLICE_IDX_A55C1         3U
+#define PWR_MEM_SLICE_IDX_A55C2         4U
+#define PWR_MEM_SLICE_IDX_A55C3         5U
+#define PWR_MEM_SLICE_IDX_A55C4         6U
+#define PWR_MEM_SLICE_IDX_A55C5         7U
+#define PWR_MEM_SLICE_IDX_A55P          8U
+#define PWR_MEM_SLICE_IDX_A55L3         9U
+#define PWR_MEM_SLICE_IDX_DDR           10U
+#define PWR_MEM_SLICE_IDX_DISPLAY       11U
+#define PWR_MEM_SLICE_IDX_GPU           12U
+#define PWR_MEM_SLICE_IDX_HSIO          13U
+#define PWR_MEM_SLICE_IDX_M7            14U
+#define PWR_MEM_SLICE_IDX_NETC          15U
+#define PWR_MEM_SLICE_IDX_NOC1          16U
+#define PWR_MEM_SLICE_IDX_NOC2          17U
+#define PWR_MEM_SLICE_IDX_NPU           18U
+#define PWR_MEM_SLICE_IDX_VPU           19U
+#define PWR_MEM_SLICE_IDX_WAKEUP        20U
+
 #endif /* ZEPHYR_NXP_IMX95_SCMI_CPU_SOC_H_ */