max32: cpu_freq: Add CPU freq support to MAX32655

Define P-states for Max32 and add cpu_freq driver
for MAX32655.

Signed-off-by: Sean Kyer <[email protected]>

Author: seankyer

boards/adi/max32655fthr/max32655fthr_max32655_m4.dts

@@ -96,6 +96,24 @@
 				<1 0 &gpio2 1 0>,   /* AIN1 */
 				<0 0 &gpio2 0 0>;   /* AIN0 */
 	};
+
+	performance-states {
+		pstate_0: pstate_0 {
+			compatible = "adi,max32-pstate";
+			load-threshold = <50>;
+			pstate-id = <0>;
+		};
+		pstate_1: pstate_1 {
+			compatible = "adi,max32-pstate";
+			load-threshold = <20>;
+			pstate-id = <1>;
+		};
+		pstate_2: pstate_2 {
+			compatible = "adi,max32-pstate";
+			load-threshold = <0>;
+			pstate-id = <2>;
+		};
+	};
 };
 
 &uart0 {

dts/bindings/p_state/adi,max32-pstate.yaml

@@ -0,0 +1,16 @@
+# Copyright (c) 2025 Analog Devices, Inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+description: Max32 custom properties for performance state (pstate)
+
+compatible: "adi,max32-pstate"
+
+include: "zephyr,pstate.yaml"
+
+properties:
+  pstate-id:
+    type: int
+    required: true
+    description: |
+      Identifier of performance state which maps to a divider setting.

samples/subsys/cpu_freq/on_demand/sample.yaml

@@ -4,3 +4,5 @@ sample:
 tests:
   sample.cpu_freq:
     tags: cpu_freq
+    platform_allow:
+      - max32655fthr/max32655/m4

soc/adi/max32/CMakeLists.txt

@@ -14,3 +14,8 @@ if(CONFIG_SOC_MAX78000 OR CONFIG_SOC_MAX78002)
 endif()
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
+
+if(CONFIG_SOC_MAX32655)
+ zephyr_library_sources_ifdef(CONFIG_CPU_FREQ max32655/cpu_freq.c)
+ zephyr_include_directories(max32655)
+endif()

soc/adi/max32/max32655/cpu_freq.c

@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/devicetree.h>
+#include <zephyr/cpu_freq/cpu_freq.h>
+#include <zephyr/cpu_freq/pstate.h>
+#include <zephyr/logging/log.h>
+
+#include "mxc_sys.h"
+
+LOG_MODULE_REGISTER(max32655_cpu_freq, CONFIG_CPU_FREQ_LOG_LEVEL);
+
+struct max32_config {
+	int state_id;
+};
+
+int32_t cpu_freq_pstate_set(struct pstate state)
+{
+	int state_id = ((const struct max32_config *)state.config)->state_id;
+
+	LOG_DBG("Setting performance state: %d", state_id);
+
+	switch (state_id) {
+	case 0:
+		LOG_DBG("Setting P-state 0: Nominal Mode");
+		break;
+	case 1:
+		LOG_DBG("Setting P-state 1: Low Power Mode");
+		break;
+	case 2:
+		LOG_DBG("Setting P-state 2: Ultra-low Power Mode");
+		break;
+	default:
+		LOG_ERR("Unsupported P-state: %d", state_id);
+		return -1;
+	}
+
+	return 0;
+}
+
+#define DEFINE_MAX32_CONFIG(node_id)                                                               \
+	static const struct max32_config _CONCAT(max32_config_, node_id) = {                       \
+		.state_id = DT_PROP(node_id, pstate_id),                                          \
+	};                                                                                         \
+	PSTATE_DT_DEFINE(node_id, &_CONCAT(max32_config_, node_id))
+
+DT_FOREACH_CHILD(DT_PATH(performance_states), DEFINE_MAX32_CONFIG)

soc/adi/max32/max32655/cpu_freq_soc.h

@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2025 Analog Devices, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_CPU_FREQ_SOC_H__
+#define ZEPHYR_CPU_FREQ_SOC_H__
+
+#include <zephyr/cpu_freq/pstate.h>
+
+/* Define performance-states as extern to be picked up by CPU Freq policy */
+#define DECLARE_PSTATE_EXTERN(node_id)                                                            \
+	extern const struct pstate _CONCAT(pstate_, DEVICE_DT_NAME_GET(node_id));
+
+DT_FOREACH_CHILD(DT_PATH(performance_states), DECLARE_PSTATE_EXTERN)
+
+#endif /* ZEPHYR_CPU_FREQ_SOC_H__ */