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54 | 54 | #define HFXO_NODE DT_NODELABEL(hfxo)
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55 | 55 |
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56 | 56 | /* LFXO config from DT */
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| 57 | +#if DT_NODE_HAS_STATUS_OKAY(LFXO_NODE) |
| 58 | +BUILD_ASSERT(DT_NODE_HAS_PROP(LFXO_NODE, load_capacitors)); |
| 59 | +#define LFXO_PIN_SEL NRF_GPIO_PIN_SEL_PERIPHERAL |
57 | 60 | #if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, external)
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58 | 61 | #define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_EXTERNAL
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59 | 62 | #elif DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal)
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60 | 63 | #define LFXO_CAP (DT_ENUM_IDX(LFXO_NODE, load_capacitance_picofarad) + 1U)
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| 64 | +#endif /*DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, external) */ |
61 | 65 | #else
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62 |
| -/* LFXO config from legacy Kconfig */ |
63 |
| -#if defined(CONFIG_SOC_LFXO_CAP_INT_6PF) |
64 |
| -#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_6PF |
65 |
| -#elif defined(CONFIG_SOC_LFXO_CAP_INT_7PF) |
66 |
| -#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_7PF |
67 |
| -#elif defined(CONFIG_SOC_LFXO_CAP_INT_9PF) |
68 |
| -#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_9PF |
69 |
| -#else |
70 |
| -#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_EXTERNAL |
71 |
| -#endif |
72 |
| -#endif |
| 66 | +#define LFXO_PIN_SEL NRF_GPIO_PIN_SEL_APP |
| 67 | +#endif /* DT_NODE_HAS_STATUS_OKAY(LFXO_NODE) */ |
73 | 68 |
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74 | 69 | /* HFXO config from DT */
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75 | 70 | #if DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, internal)
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@@ -496,17 +491,17 @@ void soc_early_init_hook(void)
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496 | 491 | #endif
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497 | 492 |
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498 | 493 | #ifdef CONFIG_SOC_NRF5340_CPUAPP
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499 |
| -#if defined(LFXO_CAP) |
| 494 | +#if DT_NODE_HAS_STATUS_OKAY(LFXO_NODE) |
500 | 495 | nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, LFXO_CAP);
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501 | 496 | #if !defined(CONFIG_BUILD_WITH_TFM)
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502 | 497 | /* This can only be done from secure code.
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503 | 498 | * This is handled by the TF-M platform so we skip it when TF-M is
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504 | 499 | * enabled.
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505 | 500 | */
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506 |
| - nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL); |
507 |
| - nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL); |
| 501 | + nrf_gpio_pin_control_select(PIN_XL1, LFXO_PIN_SEL); |
| 502 | + nrf_gpio_pin_control_select(PIN_XL2, LFXO_PIN_SEL); |
508 | 503 | #endif /* !defined(CONFIG_BUILD_WITH_TFM) */
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509 |
| -#endif /* defined(LFXO_CAP) */ |
| 504 | +#endif /* DT_NODE_HAS_STATUS_OKAY(LFXO_NODE) */ |
510 | 505 | #if defined(HFXO_CAP_VAL_X2)
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511 | 506 | /* This register is only accessible from secure code. */
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512 | 507 | uint32_t xosc32mtrim = soc_secure_read_xosc32mtrim();
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