soc: nordic: nrf53: assign pin xl1,xl2 to app core if lfxo disabled

Fixes #92663

Disabled LFXO via devicetree or kconfig allows pin 0.00 and 0.01 to work
correctly as gpio by assigning it to the app core instead of peripheral.

Signed-off-by: Ivy Lu <[email protected]>

Author: ivynya

soc/nordic/nrf53/soc.c

@@ -54,22 +54,14 @@
 #define HFXO_NODE DT_NODELABEL(hfxo)
 
 /* LFXO config from DT */
+#if DT_NODE_HAS_STATUS_OKAY(LFXO_NODE)
+BUILD_ASSERT(DT_NODE_HAS_PROP(LFXO_NODE, load_capacitors));
 #if DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, external)
 #define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_EXTERNAL
 #elif DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, internal)
 #define LFXO_CAP (DT_ENUM_IDX(LFXO_NODE, load_capacitance_picofarad) + 1U)
-#else
-/* LFXO config from legacy Kconfig */
-#if defined(CONFIG_SOC_LFXO_CAP_INT_6PF)
-#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_6PF
-#elif defined(CONFIG_SOC_LFXO_CAP_INT_7PF)
-#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_7PF
-#elif defined(CONFIG_SOC_LFXO_CAP_INT_9PF)
-#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_9PF
-#else
-#define LFXO_CAP NRF_OSCILLATORS_LFXO_CAP_EXTERNAL
-#endif
-#endif
+#endif /*DT_ENUM_HAS_VALUE(LFXO_NODE, load_capacitors, external) */
+#endif /* DT_NODE_HAS_STATUS_OKAY(LFXO_NODE) */
 
 /* HFXO config from DT */
 #if DT_ENUM_HAS_VALUE(HFXO_NODE, load_capacitors, internal)
@@ -496,7 +488,7 @@ void soc_early_init_hook(void)
 #endif
 
 #ifdef CONFIG_SOC_NRF5340_CPUAPP
-#if defined(LFXO_CAP)
+#if DT_NODE_HAS_STATUS_OKAY(LFXO_NODE)
 	nrf_oscillators_lfxo_cap_set(NRF_OSCILLATORS, LFXO_CAP);
 #if !defined(CONFIG_BUILD_WITH_TFM)
 	/* This can only be done from secure code.
@@ -506,7 +498,10 @@ void soc_early_init_hook(void)
 	nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_PERIPHERAL);
 	nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_PERIPHERAL);
 #endif /* !defined(CONFIG_BUILD_WITH_TFM) */
-#endif /* defined(LFXO_CAP) */
+#elif !defined(CONFIG_BUILD_WITH_TFM)
+	nrf_gpio_pin_control_select(PIN_XL1, NRF_GPIO_PIN_SEL_APP);
+	nrf_gpio_pin_control_select(PIN_XL2, NRF_GPIO_PIN_SEL_APP);
+#endif /* DT_NODE_HAS_STATUS_OKAY(LFXO_NODE) */
 #if defined(HFXO_CAP_VAL_X2)
 	/* This register is only accessible from secure code. */
 	uint32_t xosc32mtrim = soc_secure_read_xosc32mtrim();