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yongxu-wang15yongxu-wang15
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soc: nxp: imx95: setup m7mix and wakeupmix power on in suspend mode
wakeupmix keep power on state is essential for system suspend mode, because of console uart locate in it. temporarily set the M7 mix to power on, further optimization will be carried out later Signed-off-by: Yongxu Wang <[email protected]>
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‎soc/nxp/imx/imx9/imx95/m7/soc.c

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@@ -88,10 +88,41 @@ static int soc_init(void)
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return ret;
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}
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void pm_state_before(void)
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{
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struct scmi_cpu_pd_lpm_config cpu_pd_lpm_cfg;
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/*
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* 1. Set M7 mix as power on state in suspend mode
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* 2. Keep wakeupmix power on whatever low power mode, as lpuart3(console) in there.
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* To do: in order to reduce power consumption, the M7 core in the i.MX95
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* should be powered down during suspend.
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* However, after being woken up by a wakeup source, the M7 CPU will restart
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* execution from the vector table address, which is not the desired behavior.
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* Instead, the vector value should be set to the address where the CPU
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* was before entering suspend, and the CPU state should be restored to
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* what it was prior to suspend.
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*/
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cpu_pd_lpm_cfg.cpu_id = CPU_IDX_M7P;
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cpu_pd_lpm_cfg.num_cfg = 2;
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cpu_pd_lpm_cfg.cfgs[0].domainId = PWR_MIX_SLICE_IDX_M7;
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cpu_pd_lpm_cfg.cfgs[0].lpmSetting = SCMI_CPU_LPM_SETTING_ON_ALWAYS;
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cpu_pd_lpm_cfg.cfgs[0].retMask = 1U << PWR_MEM_SLICE_IDX_M7;
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cpu_pd_lpm_cfg.cfgs[1].domainId = PWR_MIX_SLICE_IDX_WAKEUP;
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cpu_pd_lpm_cfg.cfgs[1].lpmSetting = SCMI_CPU_LPM_SETTING_ON_ALWAYS;
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cpu_pd_lpm_cfg.cfgs[1].retMask = 0;
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scmi_cpu_pd_lpm_set(&cpu_pd_lpm_cfg);
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}
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void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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struct scmi_cpu_sleep_mode_config cpu_cfg = {0};
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pm_state_before();
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/* iMX95 M7 core is based on ARMv7-M architecture. For this architecture,
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* the current implementation of arch_irq_lock of zephyr is based on BASEPRI,
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* which will only retain abnormal interrupts such as NMI,

‎soc/nxp/imx/imx9/imx95/scmi_cpu_soc.h

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@@ -23,4 +23,85 @@
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#define CPU_SLEEP_MODE_STOP 2U
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#define CPU_SLEEP_MODE_SUSPEND 3U
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/*!
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* @name SCMI CPU LPM settings
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*/
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#define SCMI_CPU_LPM_SETTING_ON_NEVER 0U
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#define SCMI_CPU_LPM_SETTING_ON_RUN 1U
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#define SCMI_CPU_LPM_SETTING_ON_RUN_WAIT 2U
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#define SCMI_CPU_LPM_SETTING_ON_RUN_WAIT_STOP 3U
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#define SCMI_CPU_LPM_SETTING_ON_ALWAYS 4U
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#define CPU_PER_LPI_IDX_GPIO1 0U
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#define CPU_PER_LPI_IDX_GPIO2 1U
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#define CPU_PER_LPI_IDX_GPIO3 2U
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#define CPU_PER_LPI_IDX_GPIO4 3U
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#define CPU_PER_LPI_IDX_GPIO5 4U
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#define CPU_PER_LPI_IDX_CAN1 5U
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#define CPU_PER_LPI_IDX_CAN2 6U
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#define CPU_PER_LPI_IDX_CAN3 7U
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#define CPU_PER_LPI_IDX_CAN4 8U
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#define CPU_PER_LPI_IDX_CAN5 9U
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#define CPU_PER_LPI_IDX_LPUART1 10U
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#define CPU_PER_LPI_IDX_LPUART2 11U
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#define CPU_PER_LPI_IDX_LPUART3 12U
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#define CPU_PER_LPI_IDX_LPUART4 13U
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#define CPU_PER_LPI_IDX_LPUART5 14U
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#define CPU_PER_LPI_IDX_LPUART6 15U
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#define CPU_PER_LPI_IDX_LPUART7 16U
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#define CPU_PER_LPI_IDX_LPUART8 17U
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#define CPU_PER_LPI_IDX_WDOG3 18U
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#define CPU_PER_LPI_IDX_WDOG4 19U
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#define CPU_PER_LPI_IDX_WDOG5 20U
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/* MIX definitions */
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#define PWR_NUM_MIX_SLICE 23U
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#define PWR_MIX_SLICE_IDX_ANA 0U
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#define PWR_MIX_SLICE_IDX_AON 1U
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#define PWR_MIX_SLICE_IDX_BBSM 2U
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#define PWR_MIX_SLICE_IDX_CAMERA 3U
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#define PWR_MIX_SLICE_IDX_CCMSRCGPC 4U
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#define PWR_MIX_SLICE_IDX_A55C0 5U
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#define PWR_MIX_SLICE_IDX_A55C1 6U
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#define PWR_MIX_SLICE_IDX_A55C2 7U
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#define PWR_MIX_SLICE_IDX_A55C3 8U
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#define PWR_MIX_SLICE_IDX_A55C4 9U
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#define PWR_MIX_SLICE_IDX_A55C5 10U
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#define PWR_MIX_SLICE_IDX_A55P 11U
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#define PWR_MIX_SLICE_IDX_DDR 12U
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#define PWR_MIX_SLICE_IDX_DISPLAY 13U
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#define PWR_MIX_SLICE_IDX_GPU 14U
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#define PWR_MIX_SLICE_IDX_HSIO_TOP 15U
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#define PWR_MIX_SLICE_IDX_HSIO_WAON 16U
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#define PWR_MIX_SLICE_IDX_M7 17U
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#define PWR_MIX_SLICE_IDX_NETC 18U
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#define PWR_MIX_SLICE_IDX_NOC 19U
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#define PWR_MIX_SLICE_IDX_NPU 20U
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#define PWR_MIX_SLICE_IDX_VPU 21U
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#define PWR_MIX_SLICE_IDX_WAKEUP 22U
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#define PWR_MEM_SLICE_IDX_AON 0U
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#define PWR_MEM_SLICE_IDX_CAMERA 1U
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#define PWR_MEM_SLICE_IDX_A55C0 2U
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#define PWR_MEM_SLICE_IDX_A55C1 3U
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#define PWR_MEM_SLICE_IDX_A55C2 4U
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#define PWR_MEM_SLICE_IDX_A55C3 5U
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#define PWR_MEM_SLICE_IDX_A55C4 6U
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#define PWR_MEM_SLICE_IDX_A55C5 7U
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#define PWR_MEM_SLICE_IDX_A55P 8U
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#define PWR_MEM_SLICE_IDX_A55L3 9U
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#define PWR_MEM_SLICE_IDX_DDR 10U
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#define PWR_MEM_SLICE_IDX_DISPLAY 11U
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#define PWR_MEM_SLICE_IDX_GPU 12U
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#define PWR_MEM_SLICE_IDX_HSIO 13U
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#define PWR_MEM_SLICE_IDX_M7 14U
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#define PWR_MEM_SLICE_IDX_NETC 15U
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#define PWR_MEM_SLICE_IDX_NOC1 16U
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#define PWR_MEM_SLICE_IDX_NOC2 17U
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#define PWR_MEM_SLICE_IDX_NPU 18U
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#define PWR_MEM_SLICE_IDX_VPU 19U
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#define PWR_MEM_SLICE_IDX_WAKEUP 20U
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#endif /* ZEPHYR_NXP_IMX95_SCMI_CPU_SOC_H_ */

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