Commands

Command Lists

• add_hdl_source()

add_hdl_source()

Add HDL source file VHDL, Verilog or SystemVerilog to project.

add_hdl_source(hdl_source_file
    [NAME hdl_name]
    [TYPE hdl_type]
    [SOURCE hdl_source_file]
    [TARGET hdl_target_name]
    [LIBRARY hdl_library_name]
    [PACKAGE <TRUE|FALSE>]
    [ANALYSIS <TRUE|FALSE|tool_name>...]
    [SYNTHESIZABLE <TRUE|FALSE>]
    [MODELSIM_LINT <TRUE|FALSE>]
    [MODELSIM_PEDANTICERRORS <TRUE|FALSE>]
    [MODELSIM_WARNINGS_AS_ERROR <TRUE|FALSE>]
    [OUTPUT_LIBRARIES var]
    [OUTPUT_INCLUDES var]
    [OUTPUT_WORKING_DIRECTORY var]
)

Properties

• NAME

HDL module name. If not provided, HDL name will be taken from HDL source file name without file type extension. Good HDL practice is to keep HDL module name exactly as HDL source file name and only single declared HDL module per single file. HDL name should be unique and global to avoid name clashed in current project and imported (re-used) in other projects.

• ANALYSIS

Enable or disable HDL source file analysis using different simulation, lint or synthesis tool. On default this property is set to FALSE. When set to TRUE it will use all detected tools for analyzing HDL source file. You can choose one or more analysis tool separate by whitespaces. Available options:

• Vivado
• Quartus
• ModelSim
• Verilator

Example:

add_hdl_source(my_hdl_module_1.sv
    ANALYSIS
        ModelSim Quartus
)

add_hdl_source(my_hdl_module_2.sv
    ANALYSIS
        TRUE
)