Commands

add_hdl_source(``)

Add HDL source file VHDL, Verilog or SystemVerilog to project.

add_hdl_source(hdl_source_file [NAME hdl_name] [TYPE hdl_type] [SOURCE hdl_source_file] [TARGET hdl_target_name] [LIBRARY hdl_library_name] [PACKAGE <TRUE|FALSE>] [ANALYSIS <TRUE|FALSE|tool_name>...] [SYNTHESIZABLE <TRUE|FALSE>] [MODELSIM_LINT <TRUE|FALSE>] [MODELSIM_PEDANTICERRORS <TRUE|FALSE>] [MODELSIM_WARNINGS_AS_ERROR <TRUE|FALSE>] [OUTPUT_LIBRARIES var] [OUTPUT_INCLUDES var] [OUTPUT_WORKING_DIRECTORY var] )