Implement LPUART1 clock source changing.

Author: romixlab

Cargo.toml

@@ -203,3 +203,7 @@ required-features = ["rt"]
 [[example]]
 name = "adc_dma"
 required-features = ["rt"]
+
+[[example]]
+name = "serial_lpuart1_rtic"
+required-features = ["rt", "stm32l476"]

examples/serial_lpuart1_rtic.rs

@@ -0,0 +1,110 @@
+#![no_main]
+#![no_std]
+
+extern crate panic_rtt_target;
+
+use heapless::{consts::U8, spsc};
+use nb::block;
+use rtt_target::{rprint, rprintln};
+use stm32l4xx_hal::{
+    pac::{self, LPUART1},
+    prelude::*,
+    serial::{self, Config, Serial},
+};
+
+#[rtic::app(device = stm32l4xx_hal::pac)]
+const APP: () = {
+    struct Resources {
+        rx: serial::Rx<LPUART1>,
+        tx: serial::Tx<LPUART1>,
+        //
+        // rx_prod: spsc::Producer<'static, u8, U8>,
+        // rx_cons: spsc::Consumer<'static, u8, U8>,
+    }
+
+    #[init]
+    fn init(_: init::Context) -> init::LateResources {
+        static mut RX_QUEUE: spsc::Queue<u8, U8> = spsc::Queue(heapless::i::Queue::new());
+
+        rtt_target::rtt_init_print!();
+        rprint!("Initializing... ");
+
+        let p = pac::Peripherals::take().unwrap();
+
+        let mut rcc = p.RCC.constrain();
+        let mut flash = p.FLASH.constrain();
+        let mut pwr = p.PWR.constrain(&mut rcc.apb1r1);
+
+        let clocks = rcc.cfgr.freeze(&mut flash.acr, &mut pwr);
+
+        let mut gpioa = p.GPIOA.split(&mut rcc.ahb2);
+        let mut gpioc = p.GPIOC.split(&mut rcc.ahb2);
+
+        let tx_pin = gpioc
+            .pc1
+            .into_alternate(&mut gpioc.moder, &mut gpioc.otyper, &mut gpioc.afrl);
+        let rx_pin = gpioc
+            .pc0
+            .into_alternate(&mut gpioc.moder, &mut gpioc.otyper, &mut gpioc.afrl);
+
+        let mut serial = Serial::lpuart1(
+            p.LPUART1,
+            (tx_pin, rx_pin),
+            Config::default().baudrate(115_200.bps()),
+            clocks,
+            &mut rcc.apb1r2,
+        );
+        serial.listen(serial::Event::Rxne);
+
+        let (tx, rx) = serial.split();
+        let (rx_prod, rx_cons) = RX_QUEUE.split();
+
+        rprintln!("done.");
+
+        init::LateResources {
+            rx,
+            tx,
+            //
+            // rx_prod,
+            // rx_cons,
+        }
+    }
+
+    #[idle(resources = [tx])]
+    fn idle(cx: idle::Context) -> ! {
+        // let rx = cx.resources.rx_cons;
+        let tx = cx.resources.tx;
+
+        loop {
+            // if let Some(b) = rx.dequeue() {
+            //     rprintln!("Echoing '{}'", b as char);
+            //     block!(tx.write(b)).unwrap();
+            // }
+            block!(tx.write('x' as u8)).unwrap();
+            cortex_m::asm::delay(1_000_000);
+        }
+    }
+
+    #[task(binds = LPUART1, resources = [rx])]
+    fn usart2(cx: usart2::Context) {
+        let rx = cx.resources.rx;
+        // let queue = cx.resources.rx_prod;
+
+        let b = match rx.read() {
+            Ok(b) => {
+                rprintln!("Read: {}", b);
+            },
+            Err(err) => {
+                rprintln!("Error reading from USART: {:?}", err);
+                return;
+            }
+        };
+        // match queue.enqueue(b) {
+        //     Ok(()) => (),
+        //     Err(err) => {
+        //         rprintln!("Error adding received byte to queue: {:?}", err);
+        //         return;
+        //     }
+        // }
+    }
+};

src/rcc.rs

@@ -89,6 +89,7 @@ impl RccExt for RCC {
                 sysclk: None,
                 pll_source: None,
                 pll_config: None,
+                lpuart1_src: LpUart1ClockSource::Pclk,
             },
         }
     }
@@ -158,6 +159,14 @@ impl CRRCR {
     }
 }
 
+#[derive(PartialEq, Eq, Copy, Clone, Debug)]
+pub enum LpUart1ClockSource {
+    Pclk = 0b00,
+    Sysclk = 0b01,
+    Hsi16 = 0b10,
+    Lsi = 0b11
+}
+
 /// Peripherals independent clock configuration register
 pub struct CCIPR {
     _0: (),
@@ -355,6 +364,7 @@ pub struct CFGR {
     sysclk: Option<u32>,
     pll_source: Option<PllSource>,
     pll_config: Option<PllConfig>,
+    lpuart1_src: LpUart1ClockSource,
 }
 
 impl CFGR {
@@ -431,6 +441,12 @@ impl CFGR {
         self
     }
 
+    /// Sets LPUART1 clock source
+    pub fn lpuart1_clk_src(mut self, source: LpUart1ClockSource) -> Self {
+        self.lpuart1_src = source;
+        self
+    }
+
     /// Freezes the clock configuration, making it effective
     pub fn freeze(&self, acr: &mut ACR, pwr: &mut Pwr) -> Clocks {
         let rcc = unsafe { &*RCC::ptr() };
@@ -608,8 +624,18 @@ impl CFGR {
         };
 
         // Check if HSI should be started
-        if pll_source == PllSource::HSI16 || (self.msi.is_none() && self.hse.is_none()) {
-            rcc.cr.write(|w| w.hsion().set_bit());
+        let lpuart1_clk_from_hsi = match self.lpuart1_src {
+            LpUart1ClockSource::Hsi16 => {
+                rcc.ccipr.modify(|_, w| unsafe { w.lpuart1sel().bits(self.lpuart1_src as u8) });
+                true
+            }
+            LpUart1ClockSource::Lsi => {
+                todo!()
+            }
+            _ => false,
+        };
+        if pll_source == PllSource::HSI16 || (self.msi.is_none() && self.hse.is_none()) || lpuart1_clk_from_hsi {
+            rcc.cr.modify(|_, w| w.hsion().set_bit());
             while rcc.cr.read().hsirdy().bit_is_clear() {}
         }
 
@@ -819,6 +845,7 @@ impl CFGR {
             timclk1: timclk1.Hz(),
             timclk2: timclk2.Hz(),
             pll_source: pllconf.map(|_| pll_source),
+            lpuart1_src: self.lpuart1_src
         }
     }
 }
@@ -918,6 +945,7 @@ pub struct Clocks {
     timclk1: Hertz,
     timclk2: Hertz,
     pll_source: Option<PllSource>,
+    lpuart1_src: LpUart1ClockSource,
 }
 
 impl Clocks {
@@ -986,4 +1014,8 @@ impl Clocks {
     pub fn timclk2(&self) -> Hertz {
         self.timclk2
     }
+
+    pub fn lpuart1_src(&self) -> LpUart1ClockSource {
+        self.lpuart1_src
+    }
 }

src/serial.rs

@@ -298,7 +298,13 @@ macro_rules! hal {
                         }
                     },
                     {
-                        let fck = clocks.$pclkX().raw();
+                        use crate::rcc::LpUart1ClockSource;
+                        let fck = match clocks.lpuart1_src() {
+                            LpUart1ClockSource::Pclk => clocks.$pclkX().raw(),
+                            LpUart1ClockSource::Sysclk => clocks.sysclk().raw(),
+                            LpUart1ClockSource::Hsi16 => 16_000_000,
+                            LpUart1ClockSource::Lsi => 32_768,
+                        };
                         assert!((fck >= 3 * config.baudrate.0) && (fck <= 4096 * config.baudrate.0), "impossible baud rate");
                         let brr = 256u64 * (fck as u64) / config.baudrate.0 as u64;
                         let brr = brr as u32;