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Commit ddc8b38

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Fix lint errors
1 parent f153a04 commit ddc8b38

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4 files changed

+8
-9
lines changed

4 files changed

+8
-9
lines changed

arg_lut.csv

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -102,4 +102,4 @@
102102
"rd_n0_e", 11, 8
103103
"c_rs2_e", 6, 3
104104
"rd_e", 11, 8
105-
"rs2_e", 24, 21
105+
"rs2_e", 24, 21

constants.py

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -144,14 +144,14 @@ def read_arg_lut_csv(filename: str) -> "dict[str, tuple[int, int]]":
144144
"c_uimm9sphi": "uimm[5]",
145145
"c_uimm10sp_s": "uimm[5:4$\\vert$9:6]",
146146
"c_uimm9sp_s": "uimm[5:3$\\vert$8:6]",
147+
"rd_p_e": "rd\\,$'$, even values only",
148+
"rs2_p_e": "rs2\\,$'$, even values only",
149+
"rd_n0_e": "rd$\\neq$0, even values only",
150+
"c_rs2_e": "rs2, even values only",
151+
"rd_e": "rd, even values only",
152+
"rs2_e": "rs2, even values only",
147153
}
148154

149-
latex_mapping['rd_p_e'] = "rd\\,$'$, even values only"
150-
latex_mapping['rs2_p_e'] = "rs2\\,$'$, even values only"
151-
latex_mapping['rd_n0_e'] = 'rd$\\neq$0, even values only'
152-
latex_mapping['c_rs2_e'] = 'rs2, even values only'
153-
latex_mapping['rd_e'] = 'rd, even values only'
154-
latex_mapping['rs2_e'] = 'rs2, even values only'
155155

156156
# created a dummy instruction-dictionary like dictionary for all the instruction
157157
# types so that the same logic can be used to create their tables

unratified/rv32_zclsd

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7,4 +7,3 @@ $pseudo_op rv32_c_f::c.fsw c.sd rs1_p rs2_p_e c_uimm8hi c_uimm8lo 2..0=0 15..
77
#quadrant 2
88
$pseudo_op rv32_c_f::c.flwsp c.ldsp rd_n0_e c_uimm9sphi c_uimm9splo 1..0=2 15..13=3 7=0
99
$pseudo_op rv32_c_f::c.fswsp c.sdsp c_rs2_e c_uimm9sp_s 2..0=2 15..13=7
10-

unratified/rv32_zilsd

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
11
# Load/store pair for RV32
22

33
ld rd_e rs1 imm12 14..12=3 7..2=0x00 1..0=3
4-
sd imm12hi rs1 rs2_e imm12lo 20=0 14..12=3 6..2=0x08 1..0=3
4+
sd imm12hi rs1 rs2_e imm12lo 20=0 14..12=3 6..2=0x08 1..0=3

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