Change zimm variable to zimm5, since they were exactly the same. Fixes #342. (#347)

Signed-off-by: Afonso Oliveira <[email protected]>

Author: AFOliveira

extensions/rv_f

@@ -37,9 +37,9 @@ $pseudo_op rv_f::fsgnjn.s fneg.s  rd rs1 rs2=rs1 31..27=0x04 14..12=1 26..25=0 6
 #CSRs
 $pseudo_op rv_zicsr::csrrs  frflags    rd 19..15=0 31..20=0x001 14..12=2 6..2=0x1C 1..0=3
 $pseudo_op rv_zicsr::csrrw  fsflags    rd rs1      31..20=0x001 14..12=1 6..2=0x1C 1..0=3
-$pseudo_op rv_zicsr::csrrwi fsflagsi   rd zimm     31..20=0x001 14..12=5 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrwi fsflagsi   rd zimm5     31..20=0x001 14..12=5 6..2=0x1C 1..0=3
 $pseudo_op rv_zicsr::csrrs  frrm       rd 19..15=0 31..20=0x002 14..12=2 6..2=0x1C 1..0=3
 $pseudo_op rv_zicsr::csrrw  fsrm       rd rs1      31..20=0x002 14..12=1 6..2=0x1C 1..0=3
-$pseudo_op rv_zicsr::csrrwi fsrmi      rd zimm     31..20=0x002 14..12=5 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrwi fsrmi      rd zimm5     31..20=0x002 14..12=5 6..2=0x1C 1..0=3
 $pseudo_op rv_zicsr::csrrw  fscsr      rd rs1      31..20=0x003 14..12=1 6..2=0x1C 1..0=3
 $pseudo_op rv_zicsr::csrrs  frcsr      rd 19..15=0 31..20=0x003 14..12=2 6..2=0x1C 1..0=3

extensions/rv_v

@@ -8,7 +8,7 @@
 
 # configuration setting
 # https://github.com/riscv/riscv-v-spec/blob/master/vcfg-format.adoc
-vsetivli     31=1 30=1 zimm10    zimm 14..12=0x7 rd 6..0=0x57
+vsetivli     31=1 30=1 zimm10    zimm5 14..12=0x7 rd 6..0=0x57
 vsetvli      31=0 zimm11          rs1 14..12=0x7 rd 6..0=0x57
 vsetvl       31=1 30..25=0x0 rs2  rs1 14..12=0x7 rd 6..0=0x57
 

extensions/rv_zicsr

@@ -1,15 +1,15 @@
 csrrw     rd rs1 csr        14..12=1 6..2=0x1C 1..0=3
 csrrs     rd rs1 csr        14..12=2 6..2=0x1C 1..0=3
 csrrc     rd rs1 csr        14..12=3 6..2=0x1C 1..0=3
-csrrwi    rd csr zimm       14..12=5 6..2=0x1C 1..0=3
-csrrsi    rd csr zimm       14..12=6 6..2=0x1C 1..0=3
-csrrci    rd csr zimm       14..12=7 6..2=0x1C 1..0=3
+csrrwi    rd csr zimm5       14..12=5 6..2=0x1C 1..0=3
+csrrsi    rd csr zimm5       14..12=6 6..2=0x1C 1..0=3
+csrrci    rd csr zimm5       14..12=7 6..2=0x1C 1..0=3
 
 #pseudoinstructions
 $pseudo_op rv_zicsr::csrrs csrr     rd csr      19..15=0x0 14..12=2 6..2=0x1C 1..0=3
 $pseudo_op rv_zicsr::csrrw csrw     rs1 csr     14..12=1 11..7=0x0 6..2=0x1C 1..0=3
 $pseudo_op rv_zicsr::csrrs csrs     rs1 csr     14..12=2 11..7=0x0 6..2=0x1C 1..0=3
 $pseudo_op rv_zicsr::csrrc csrc     rs1 csr     14..12=3 11..7=0x0 6..2=0x1C 1..0=3
-$pseudo_op rv_zicsr::csrrwi csrwi   csr zimm    14..12=5 11..7=0x0 6..2=0x1C 1..0=3
-$pseudo_op rv_zicsr::csrrsi csrsi   csr zimm    14..12=6 11..7=0x0 6..2=0x1C 1..0=3
-$pseudo_op rv_zicsr::csrrci csrci   csr zimm    14..12=7 11..7=0x0 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrwi csrwi   csr zimm5    14..12=5 11..7=0x0 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrsi csrsi   csr zimm5    14..12=6 11..7=0x0 6..2=0x1C 1..0=3
+$pseudo_op rv_zicsr::csrrci csrci   csr zimm5    14..12=7 11..7=0x0 6..2=0x1C 1..0=3