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RISC-V ISA Build RISC-V ISA Build #1584: Manually run by wmat
June 9, 2025 17:27 5m 2s copyright
copyright
June 9, 2025 17:27 5m 2s
submodules in /. - Update #1030839376 Dependabot Updates #142: by dependabot bot
June 9, 2025 17:05 38s main
main
June 9, 2025 17:05 38s
[AdditionalVectorCrypto] adding section on addition vector crypto extensions Check Mergeable by Label #255: Pull request #1306 edited by nibrunieAtSi5
June 7, 2025 19:10 2s nibrunieAtSi5:additional-vector-crypto
nibrunieAtSi5:additional-vector-crypto
June 7, 2025 19:10 2s
fix: mstateen*h and hstateen*h access upper half of 64-bit registers Check Mergeable by Label #254: Pull request #2066 synchronize by ThinkOpenly
June 6, 2025 18:52 2s ThinkOpenly:high-half-of-64
ThinkOpenly:high-half-of-64
June 6, 2025 18:52 2s
fix: mstateen*h and hstateen*h access upper half of 64-bit registers RISC-V ISA Build #1583: Pull request #2066 synchronize by ThinkOpenly
June 6, 2025 18:52 7m 28s ThinkOpenly:high-half-of-64
ThinkOpenly:high-half-of-64
June 6, 2025 18:52 7m 28s
fix: mstateen*h and hstateen*h access upper half of 64-bit registers pre-commit #167: Pull request #2066 synchronize by ThinkOpenly
June 6, 2025 18:52 17s ThinkOpenly:high-half-of-64
ThinkOpenly:high-half-of-64
June 6, 2025 18:52 17s
submodules in /. - Update #1029545239 Dependabot Updates #141: by dependabot bot
June 6, 2025 16:49 35s main
main
June 6, 2025 16:49 35s
submodules in /. - Update #1028709451 Dependabot Updates #140: by dependabot bot
June 5, 2025 16:28 40s main
main
June 5, 2025 16:28 40s
fix: mstateen*h and hstateen*h access upper half of 64-bit registers Check Mergeable by Label #253: Pull request #2066 synchronize by ThinkOpenly
June 5, 2025 13:57 1s ThinkOpenly:high-half-of-64
ThinkOpenly:high-half-of-64
June 5, 2025 13:57 1s
fix: mstateen*h and hstateen*h access upper half of 64-bit registers RISC-V ISA Build #1582: Pull request #2066 synchronize by ThinkOpenly
June 5, 2025 13:57 7m 18s ThinkOpenly:high-half-of-64
ThinkOpenly:high-half-of-64
June 5, 2025 13:57 7m 18s
fix: mstateen*h and hstateen*h access upper half of 64-bit registers pre-commit #166: Pull request #2066 synchronize by ThinkOpenly
June 5, 2025 13:57 18s ThinkOpenly:high-half-of-64
ThinkOpenly:high-half-of-64
June 5, 2025 13:57 18s
Release New ISA When Merging a PR Release New ISA When Merging a PR #372: completed by terpstra
June 4, 2025 18:29 7m 15s
June 4, 2025 18:29 7m 15s
Correct the table for RVWMO CSR set/clear instruction dependencies (#… pre-commit #165: Commit 0fb590e pushed by terpstra
June 4, 2025 18:21 18s main
main
June 4, 2025 18:21 18s
Correct the table for RVWMO CSR set/clear instruction dependencies (#… RISC-V ISA Build #1581: Commit 0fb590e pushed by terpstra
June 4, 2025 18:21 7m 36s main
main
June 4, 2025 18:21 7m 36s
submodules in /. - Update #1027985238 Dependabot Updates #139: by dependabot bot
June 4, 2025 16:27 35s main
main
June 4, 2025 16:27 35s
fix: mstateen*h and hstateen*h access upper half of 64-bit registers Check Mergeable by Label #252: Pull request #2066 opened by ThinkOpenly
June 4, 2025 14:25 3s ThinkOpenly:high-half-of-64
ThinkOpenly:high-half-of-64
June 4, 2025 14:25 3s
fix: mstateen*h and hstateen*h access upper half of 64-bit registers RISC-V ISA Build #1580: Pull request #2066 opened by ThinkOpenly
June 4, 2025 14:25 7m 37s ThinkOpenly:high-half-of-64
ThinkOpenly:high-half-of-64
June 4, 2025 14:25 7m 37s
fix: mstateen*h and hstateen*h access upper half of 64-bit registers pre-commit #164: Pull request #2066 opened by ThinkOpenly
June 4, 2025 14:25 19s ThinkOpenly:high-half-of-64
ThinkOpenly:high-half-of-64
June 4, 2025 14:25 19s
Correct the table for RVWMO CSR set/clear instruction dependencies Check Mergeable by Label #251: Pull request #2065 edited by terpstra
June 4, 2025 04:04 2s rvwmo-fix-csr-deps
rvwmo-fix-csr-deps
June 4, 2025 04:04 2s
Correct the table for RVWMO CSR set/clear instruction dependencies pre-commit #163: Pull request #2065 synchronize by terpstra
June 4, 2025 04:03 17s rvwmo-fix-csr-deps
rvwmo-fix-csr-deps
June 4, 2025 04:03 17s
Correct the table for RVWMO CSR set/clear instruction dependencies Check Mergeable by Label #250: Pull request #2065 synchronize by terpstra
June 4, 2025 04:03 2s rvwmo-fix-csr-deps
rvwmo-fix-csr-deps
June 4, 2025 04:03 2s
Correct the table for RVWMO CSR set/clear instruction dependencies RISC-V ISA Build #1579: Pull request #2065 synchronize by terpstra
June 4, 2025 04:03 7m 9s rvwmo-fix-csr-deps
rvwmo-fix-csr-deps
June 4, 2025 04:03 7m 9s
Release New ISA When Merging a PR Release New ISA When Merging a PR #371: completed by aswaterman
June 3, 2025 22:29 7m 11s
June 3, 2025 22:29 7m 11s
fixed missing frm reg in FCVT.W.D source registers (#2064) RISC-V ISA Build #1578: Commit 55ee5e3 pushed by aswaterman
June 3, 2025 22:21 7m 44s main
main
June 3, 2025 22:21 7m 44s
fixed missing frm reg in FCVT.W.D source registers (#2064) pre-commit #162: Commit 55ee5e3 pushed by aswaterman
June 3, 2025 22:21 17s main
main
June 3, 2025 22:21 17s