Files

spi_slave_design_details.csv

uploading input files for spi_slave

Jun 28, 2019

a447eb2 · Jun 28, 2019

1	Design Name	spi_slave
2	Output Directory	outdir_spi_slave
3	Netlist Directory	verilog
4	Early Library Path	/usr/local/share/qflow/tech/osu018/osu018_stdcells.lib
5	Late Library Path	/usr/local/share/qflow/tech/osu018/osu018_stdcells.lib
6	Constraints File	spi_slave_design_constraints.csv