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lines changed- .github
- .pic
- Basic Verilog structures
- assignments
- concatenation
- controllers
- modules
- multiplexors
- registers
- Introduction
- How FPGA works
- Implementation steps
- Sequential logic
- What is HDL
- Labs
- board files
- lab_01_adder
- lab_02_alu
- lab_03_memory
- lab_04_cybercobra
- lab_06_main_memory
- lab_07_dp
- lab_08_lsu
- lab_10_irq
- lab_11_irq_integration
- lab_12_daisy_chain
- lab_13_periph
- lab_15_programming_device
- Other/rv32i
- Vivado Basics/01. New project
- Basic Verilog structures
- Introduction
- Labs
- 01. Adder
- 02. Arithmetic-logic unit
- 03. Register file and memory
- 04. Primitive programmable device
- Индивидуальное задание
- 05. Main decoder
- 06. Main memory
- 07. Datapath
- 08. Load-store unit
- 09. LSU Integration
- 10. Interrupt subsystem
- 12. Daisy chain
- 13. Peripheral units
- 14. Programming
- 15. Programming device
- 16. Coremark
- Made-up modules
- Lectures
- Other
- Vivado Basics
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