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HepoH3HepoH3
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Merge pull request #85 from Fe1LDr/master
ЛР15-16. Исправление тестбенчей.
2 parents f7ab67d + af721e3 commit 1ff71c5

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-80
lines changed

4 files changed

+138
-80
lines changed

‎Labs/15. Programming device/tb_bluster.sv

Lines changed: 15 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -65,6 +65,19 @@ module tb_blaster();
6565
instr_size = instr_mem_byte.size();
6666
data_size = data_mem_byte.size();
6767
tiff_size = tiff_mem_byte.size();
68+
69+
/*
70+
RCV_NEXT_COMMAND
71+
*/
72+
flash_addr = 32'h0000;
73+
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
74+
tx_data = flash_addr[i];
75+
tx_valid = 1'b1;
76+
@(posedge clk_i);
77+
tx_valid = 1'b0;
78+
@(posedge clk_i);
79+
while(tx_busy) @(posedge clk_i);
80+
end
6881

6982
/*
7083
INIT_MSG
@@ -317,7 +330,7 @@ module tb_blaster();
317330
while(tx_busy) @(posedge clk_i);
318331
end
319332

320-
assert(!pc_reset_o)
333+
assert(!core_reset_o)
321334
else $error("reset is not equal zero at the end");
322335
// ----------------------------------------------
323336

@@ -355,7 +368,7 @@ uart_tx tx(
355368

356369
rw_instr_mem imem(
357370
.clk_i (clk_i ) ,
358-
.addr_i (instr_addr_i ) ,
371+
.read_addr_i (instr_addr_i ) ,
359372
.read_data_o (instr_rdata_o ) ,
360373
.write_addr_i (instr_addr_o ) ,
361374
.write_data_i (instr_wdata_o ) ,

‎Labs/15. Programming device/tb_top_asic.sv

Lines changed: 111 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -10,58 +10,65 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
1010
*/
1111
module tb_top_asic();
1212

13-
logic clk10mhz_i;
13+
logic clk100mhz_i;
1414
logic aresetn_i;
1515
logic rx_i;
1616
logic tx_o;
17-
logic clk_i;
18-
logic rst_i;
17+
logic clk_i;
18+
logic rst_i;
1919

2020
assign aresetn_i = !rst_i;
21-
assign clk10mhz_i = clk_i;
2221

2322
logic rx_busy, rx_valid, tx_busy, tx_valid;
2423
logic [7:0] rx_data, tx_data;
2524

25+
logic [3:0] [7:0] flash_addr;
26+
logic [3:0] [7:0] instr_size;
2627
logic [3:0] [7:0] instr_size_ack;
28+
logic [3:0] [7:0] data_size;
2729
logic [3:0] [7:0] data_size_ack;
28-
logic [3:0] [7:0] tiff_size = 32'd0;
30+
logic [3:0] [7:0] tiff_size;
2931
logic [3:0] [7:0] tiff_size_ack;
30-
byte init_str[6];
31-
byte done_str[10];
32-
logic [7:0] instr_mem_byte[];
33-
logic [7:0] data_mem_byte[];
34-
logic [3:0] [7:0] instr_size;
35-
logic [3:0] [7:0] data_size;
36-
37-
initial begin
38-
// $readmemh("tb_coremark_instr.mem", instr_mem_byte);
39-
// $readmemh("tb_coremark_data.mem", data_mem_byte);
40-
// instr_size = instr_mem_byte.size();
41-
// data_size = data_mem_byte.size();
42-
instr_size = 0;
43-
data_size = 0;
44-
end
45-
46-
logic [7:0] tiff_mem_byte [2048];
47-
48-
localparam INIT_MSG_SIZE = 6;
49-
localparam MSG_DONE_SIZE = 10;
32+
33+
logic [7:0] instr_mem_byte[$];
34+
logic [7:0] data_mem_byte[$];
35+
logic [7:0] tiff_mem_byte [$];
36+
37+
localparam INIT_MSG_SIZE = 40;
38+
localparam MSG_DONE_SIZE = 57;
5039
localparam MSG_ACK_SIZE = 4;
40+
41+
byte init_str[INIT_MSG_SIZE];
42+
byte done_str[MSG_DONE_SIZE];
5143

5244
always #50ns clk_i = !clk_i;
53-
54-
byte coremark_msg[103];
55-
integer coremark_cntr;
45+
always #5ns clk100mhz_i = !clk100mhz_i;
5646

5747
initial begin
5848
$timeformat(-9, 2, " ns", 3);
5949
clk_i = 0;
50+
clk100mhz_i = 0;
6051
rst_i <= 0;
6152
@(posedge clk_i);
6253
rst_i <= 1;
6354
repeat(2) @(posedge clk_i);
6455
rst_i <= 0;
56+
instr_size = instr_mem_byte.size();
57+
data_size = data_mem_byte.size();
58+
tiff_size = tiff_mem_byte.size();
59+
60+
/*
61+
RCV_NEXT_COMMAND
62+
*/
63+
flash_addr = 32'h0000;
64+
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
65+
tx_data = flash_addr[i];
66+
tx_valid = 1'b1;
67+
@(posedge clk_i);
68+
tx_valid = 1'b0;
69+
@(posedge clk_i);
70+
while(tx_busy) @(posedge clk_i);
71+
end
6572

6673
/*
6774
INIT_MSG
@@ -138,6 +145,30 @@ module tb_top_asic();
138145
repeat(10000)@(posedge clk_i);
139146

140147

148+
/*
149+
RCV_NEXT_COMMAND
150+
*/ flash_addr = 32'h4000;
151+
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
152+
tx_data = flash_addr[i];
153+
tx_valid = 1'b1;
154+
@(posedge clk_i);
155+
tx_valid = 1'b0;
156+
@(posedge clk_i);
157+
while(tx_busy) @(posedge clk_i);
158+
end
159+
160+
161+
/*
162+
INIT_MSG
163+
*/
164+
for(int i = 0; i < INIT_MSG_SIZE; i++) begin
165+
@(posedge clk_i);
166+
while(!rx_valid)@(posedge clk_i);
167+
init_str[i] = rx_data;
168+
end
169+
$display("%s", init_str);
170+
wait(tx_o);
171+
// ----------------------------------------------
141172

142173
/*
143174
RCV_DATA_SIZE
@@ -196,8 +227,29 @@ module tb_top_asic();
196227
repeat(10000)@(posedge clk_i);
197228

198229

230+
/*
231+
RCV_NEXT_COMMAND
232+
*/ flash_addr = 32'h0800_0000;
233+
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
234+
tx_data = flash_addr[i];
235+
tx_valid = 1'b1;
236+
@(posedge clk_i);
237+
tx_valid = 1'b0;
238+
@(posedge clk_i);
239+
while(tx_busy) @(posedge clk_i);
240+
end
199241

200-
242+
/*
243+
INIT_MSG
244+
*/
245+
for(int i = 0; i < INIT_MSG_SIZE; i++) begin
246+
@(posedge clk_i);
247+
while(!rx_valid)@(posedge clk_i);
248+
init_str[i] = rx_data;
249+
end
250+
$display("%s", init_str);
251+
wait(tx_o);
252+
// ----------------------------------------------
201253

202254
/*
203255
RCV_TIFF_SIZE
@@ -254,32 +306,34 @@ module tb_top_asic();
254306
$display("%t %s", $time, done_str);
255307
wait(!rx_busy)
256308
@(posedge clk_i)
257-
// assert(!pc_stall_o)
258-
// else $error("stall is not equal zero at the end");
309+
310+
/*
311+
RCV_NEXT_COMMAND
312+
*/ flash_addr = 32'hFFFF_FFFF;
313+
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
314+
tx_data = flash_addr[i];
315+
tx_valid = 1'b1;
316+
@(posedge clk_i);
317+
tx_valid = 1'b0;
318+
@(posedge clk_i);
319+
while(tx_busy) @(posedge clk_i);
320+
end
321+
assert(!DUT.core_reset) $display("Rooom to tooom");
322+
else $error("stall is not equal zero at the end");
259323
// ----------------------------------------------
260324

261325
repeat(10000)@(posedge clk_i);
262-
coremark_cntr = 0;
263-
coremark_msg = {32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32};
264-
forever begin
265-
@(posedge clk_i);
266-
if(rx_valid) begin
267-
if((rx_data == 10) | (rx_data == 13)) begin
268-
$display("%s", coremark_msg);
269-
coremark_cntr = 0;
270-
coremark_msg = {32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32, 32};
271-
end
272-
else begin
273-
coremark_msg[coremark_cntr] = rx_data;
274-
coremark_cntr++;
275-
end
276-
end
277-
end
278-
// $finish();
326+
327+
$finish();
279328
end
280329

281330

282-
riscv_top_asic DUT(.clk10mhz_i, .aresetn_i, .rx_i, .tx_o);
331+
riscv_unit DUT(
332+
.clk_i (clk100mhz_i),
333+
.resetn_i (aresetn_i),
334+
.rx_i (rx_i),
335+
.tx_o (tx_o)
336+
);
283337

284338
uart_rx rx(
285339
.clk_i (clk_i ),
@@ -305,6 +359,14 @@ uart_tx tx(
305359
.tx_valid_i (tx_valid )
306360
);
307361

362+
initial instr_mem_byte = {
363+
8'h93, 8'h00, 8'h10, 8'h00, 8'h37, 8'h01, 8'h00, 8'h06, 8'hB7, 8'hC1, 8'h01, 8'h00, 8'h93, 8'h81, 8'h01, 8'h20,
364+
8'h23, 8'h26, 8'h31, 8'h00, 8'h13, 8'h02, 8'h10, 8'h00, 8'h23, 8'h28, 8'h41, 8'h00, 8'h93, 8'h02, 8'h10, 8'h00,
365+
8'h93, 8'h80, 8'h10, 8'h00, 8'h83, 8'h23, 8'h81, 8'h00, 8'h63, 8'h14, 8'h70, 8'h00, 8'h6F, 8'h00, 8'h00, 8'h00,
366+
8'h6F, 8'h00, 8'h00, 8'h00, 8'h23, 8'h20, 8'h11, 8'h00, 8'h6F, 8'h00, 8'h00, 8'h00
367+
};
368+
369+
initial #1 data_mem_byte = instr_mem_byte;
308370

309371
initial tiff_mem_byte = {
310372
8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00000000, 8'b00011110, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00010000, 8'b00011110,
@@ -437,27 +499,4 @@ initial tiff_mem_byte = {
437499
8'b00000000, 8'b00000011, 8'b00000101, 8'b00000101, 8'b00000011, 8'b00000000, 8'b00001100, 8'b00001100, 8'b00000100, 8'b00101100, 8'b00100000, 8'b00100000, 8'b01100000, 8'b00000000, 8'b00000000, 8'b00000000
438500
};
439501

440-
endmodule
441-
442-
443-
module rw_tiff_mem(
444-
input logic clk_i,
445-
input logic [ 31:0] addr_i,
446-
output logic [127:0] read_data_o,
447-
448-
input logic [ 31:0] write_addr_i,
449-
input logic [127:0] write_data_i,
450-
input logic write_enable_i
451-
);
452-
453-
logic [127:0] rom [256];
454-
455-
assign read_data_o = rom[addr_i];
456-
457-
always_ff @(posedge clk_i) begin
458-
if(write_enable_i) begin
459-
rom[write_addr_i] <= write_data_i;
460-
end
461-
end
462-
463502
endmodule

‎Labs/16. Coremark/tb_coremark.sv

Lines changed: 9 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -10,26 +10,27 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
1010
*/
1111
module tb_coremark();
1212

13-
logic clk10mhz_i;
13+
logic clk100mhz_i;
1414
logic aresetn_i;
1515
logic rx_i;
1616
logic tx_o;
1717
logic clk_i;
1818
logic rst_i;
1919

2020
assign aresetn_i = !rst_i;
21-
assign clk10mhz_i = clk_i;
2221

2322
logic rx_busy, rx_valid, tx_busy, tx_valid;
2423
logic [7:0] rx_data, tx_data;
2524

2625
always #50ns clk_i = !clk_i;
26+
always #5ns clk100mhz_i = !clk100mhz_i;
2727

2828
byte coremark_msg[103];
2929
integer coremark_cntr;
3030

3131
initial begin
3232
$timeformat(-9, 2, " ns", 3);
33+
clk100mhz_i = 0;
3334
clk_i = 0;
3435
rst_i <= 0;
3536
@(posedge clk_i);
@@ -58,7 +59,12 @@ module tb_coremark();
5859
end
5960

6061
initial #500ms $finish();
61-
riscv_top_asic DUT(.clk10mhz_i, .aresetn_i, .rx_i, .tx_o);
62+
riscv_unit DUT(
63+
.clk_i (clk100mhz_i),
64+
.resetn_i (aresetn_i),
65+
.rx_i (rx_i),
66+
.tx_o (tx_o)
67+
);
6268

6369
uart_rx rx(
6470
.clk_i (clk_i ),

‎Labs/16. Coremark/tb_timer.sv

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -21,9 +21,9 @@ module tb_timer();
2121
logic interrupt_request_o;
2222

2323
localparam SYS_CNT_ADDR = 32'h0000_0000;
24-
localparam DELAY_ADDR = 32'h0000_0004;
25-
localparam MODE_ADDR = 32'h0000_0008;
26-
localparam REP_CNT_ADDR = 32'h0000_000C;
24+
localparam DELAY_ADDR = 32'h0000_0008;
25+
localparam MODE_ADDR = 32'h0000_0010;
26+
localparam REP_CNT_ADDR = 32'h0000_0014;
2727
localparam RST_ADDR = 32'h0000_0024;
2828

2929
localparam OFF = 32'd0;

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