Information required: Declaration of blank_circuit in LVS check (Klayout)

[anbala90]

The LVS check for a design is not successful with IHP-open-PDK tech-based IO Cells (Filler, Corner, IO pad) and SRAM blocks using the Ruby-based LVS rules in sg13g2.lvs, even though extraction and verification over std cells are fine. It would be greatly appreciated if anyone could guide me on how to filter out SRAM macros/blocks and IO cells from the LVS check of the full-chip.

Hint: No expected results achieved while trying to add the below comments as per the Klayout guide
netlist.blank_circuit("CIRCUIT_NAME")
schematic.blank_circuit("CIRCUIT_NAME")

[d-m-bailey]

@anbala90 I'm interested in how this would be set up and am willing to invest some time into debugging. Can you share your verification data?

[anbala90]

Hello @d-m-bailey,

Thank you for your prompt response, and sorry for the delay. Please find the attached verification report.

1. IO-Filler cells and Corner cells

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 In the lvs check,  the IO-Filler cells and Corner cells are not recognized by Klayout while it extract the schematic view from CDL netlist. 

In the sub-circuit, we can see that, the Filler cells encapsulate only some PIN information.

2. IOPad cells

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In IOPad cells, both extraction, schematic and layout extraction. are successful, but with mismatched pins and nets 

3. Memory cell

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In memory cells, Klayout tool could not extract some subcircuits as in the picture below

Also, the other sub-circuits show mismatched nets and pins

[d-m-bailey]

@anbala90

Thanks for the detailed report. I'm guessing that there are some substrate issues among other things, i.e. iovss and vss may be connect via the substrate.

If you can share the following information, I'll attempt to find solutions to the problems.

1. Source netlist
2. GDS data
3. PDK version

Do you have a target tapeout date?

[anbala90]

Thank you very much for the reply. Give me some time, I will update accordingly. Yes, I have a target Tapeout on September 14.