project_1_def_val.txt

BOARD_PART:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
COMPXLIB.ACTIVEHDL_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.cache/compile_simlib/activehdl)==CURRENT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.cache/compile_simlib/activehdl)
COMPXLIB.FUNCSIM:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
COMPXLIB.IES_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.cache/compile_simlib/ies)==CURRENT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.cache/compile_simlib/ies)
COMPXLIB.MODELSIM_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.cache/compile_simlib/modelsim)==CURRENT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.cache/compile_simlib/modelsim)
COMPXLIB.OVERWRITE_LIBS:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
COMPXLIB.QUESTA_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.cache/compile_simlib/questa)==CURRENT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.cache/compile_simlib/questa)
COMPXLIB.RIVIERA_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.cache/compile_simlib/riviera)==CURRENT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.cache/compile_simlib/riviera)
COMPXLIB.TIMESIM:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
COMPXLIB.VCS_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.cache/compile_simlib/vcs)==CURRENT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.cache/compile_simlib/vcs)
COMPXLIB.XSIM_COMPILED_LIBRARY_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
CORECONTAINER.ENABLE:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
DEFAULT_LIB:(string) DEFAULT_VALUE ()==CURRENT_VALUE (xil_defaultlib)
ENABLE_OPTIONAL_RUNS_STA:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
ENABLE_VHDL_2008:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
GENERATE_IP_UPGRADE_LOG:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
IP_CACHE_PERMISSIONS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE (read write)
IP_INTERFACE_INFERENCE_PRIORITY:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
IP_OUTPUT_REPO:(string) DEFAULT_VALUE ()==CURRENT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.cache/ip)
IS_READONLY:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
LEGACY_IP_REPO_PATHS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
MEM.ENABLE_MEMORY_MAP_GENERATION:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
PART:(string) DEFAULT_VALUE ()==CURRENT_VALUE (xc7a35tcpg236-1)
PLATFORM.BOARD_ID:(string) DEFAULT_VALUE ()==CURRENT_VALUE (arty-a7-35)
PLATFORM.DEFAULT_OUTPUT_TYPE:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (undefined)
PLATFORM.DESIGN_INTENT.DATACENTER:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (undefined)
PLATFORM.DESIGN_INTENT.EMBEDDED:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (undefined)
PLATFORM.DESIGN_INTENT.EXTERNAL_HOST:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (undefined)
PLATFORM.DESIGN_INTENT.SERVER_MANAGED:(enum) DEFAULT_VALUE (undefined)==CURRENT_VALUE (undefined)
PLATFORM.ROM.DEBUG_TYPE:(int) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
PLATFORM.ROM.PROM_TYPE:(int) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
PLATFORM.SLRCONSTRAINTMODE:(int) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
PROJECT_TYPE:(enum) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
PR_FLOW:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
SIM.CENTRAL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE (/home/chao/git/FPGAIgnite-VGA/project_1/project_1.ip_user_files)
SIM.IP.AUTO_EXPORT_SCRIPTS:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (1)
SIM.USE_IP_COMPILED_LIBS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
SIMULATOR.ACTIVEHDL_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.IES_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.MODELSIM_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.QUESTA_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.RIVIERA_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.VCS_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR.XCELIUM_INSTALL_DIR:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
SIMULATOR_LANGUAGE:(enum) DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Mixed)
SOURCE_MGMT_MODE:(enum) DEFAULT_VALUE (All)==CURRENT_VALUE (DisplayOnly)
TARGET_LANGUAGE:(enum) DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
TARGET_SIMULATOR:(string) DEFAULT_VALUE (XSim)==CURRENT_VALUE (XSim)
TOOL_FLOW:(enum) DEFAULT_VALUE (Vivado)==CURRENT_VALUE (Vivado)
WEBTALK.ACTIVEHDL_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (5)
WEBTALK.IES_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (5)
WEBTALK.MODELSIM_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (5)
WEBTALK.QUESTA_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (5)
WEBTALK.RIVIERA_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (5)
WEBTALK.VCS_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (5)
WEBTALK.XSIM_EXPORT_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (5)
WEBTALK.XSIM_LAUNCH_SIM:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (2)
XPM_LIBRARIES:(string*) DEFAULT_VALUE ()==CURRENT_VALUE (XPM_CDC)
XSIM.ARRAY_DISPLAY_LIMIT:(string) DEFAULT_VALUE (1024)==CURRENT_VALUE (1024)
XSIM.RADIX:(enum) DEFAULT_VALUE (hex)==CURRENT_VALUE (hex)
XSIM.TIME_UNIT:(enum) DEFAULT_VALUE (ns)==CURRENT_VALUE (ns)
XSIM.TRACE_LIMIT:(string) DEFAULT_VALUE (65536)==CURRENT_VALUE (65536)
ppu.v=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog)
ppu.v=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ppu.v=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
ppu.v=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
ppu.v=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
ppu.v=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
ppu.v=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ppu.v=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ppu.v=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
top.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
top.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
top.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
top.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
top.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
top.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
top.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
top.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
vga_driver.v=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (Verilog)
vga_driver.v=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
vga_driver.v=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
vga_driver.v=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
vga_driver.v=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
vga_driver.v=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
vga_driver.v=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
vga_driver.v=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
vga_driver.v=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
clk_wiz_0.xci=GENERATE_FILES_FOR_REFERENCE (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (0)
clk_wiz_0.xci=GENERATE_SYNTH_CHECKPOINT (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
clk_wiz_0.xci=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
clk_wiz_0.xci=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
clk_wiz_0.xci=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
clk_wiz_0.xci=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
clk_wiz_0.xci=REGISTERED_WITH_MANAGER (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (1)
clk_wiz_0.xci=SYNTH_CHECKPOINT_MODE (enum) :DEFAULT_VALUE (None)==CURRENT_VALUE (Singular)
clk_wiz_0.xci=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation simulation)==CURRENT_VALUE (synthesis implementation simulation)
clk_wiz_0.xci=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
clk_wiz_0.xci=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
clk_wiz_0.xci=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
DESIGN_MODE:(enum) DEFAULT_VALUE (RTL)==CURRENT_VALUE (RTL)
EDIF_EXTRA_SEARCH_PATHS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
ELAB_LINK_DCPS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
ELAB_LOAD_TIMING_CONSTRAINTS:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
GENERIC:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCLUDE_DIRS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
LIB_MAP_FILE:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
LOOP_COUNT:(int) DEFAULT_VALUE (1000)==CURRENT_VALUE (1000)
NAME:(string) DEFAULT_VALUE (sources_1)==CURRENT_VALUE (sources_1)
TOP:(string) DEFAULT_VALUE ()==CURRENT_VALUE (top)
TOP_AUTO_SET:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (0)
VERILOG_DEFINE:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
VERILOG_UPPERCASE:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
VERILOG_VERSION:(enum) DEFAULT_VALUE (verilog_2001)==CURRENT_VALUE (verilog_2001)
VHDL_VERSION:(enum) DEFAULT_VALUE (vhdl_2k)==CURRENT_VALUE (vhdl_2k)
Arty_Master.xdc=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (XDC)
Arty_Master.xdc=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (0)
Arty_Master.xdc=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
Arty_Master.xdc=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
Arty_Master.xdc=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
Arty_Master.xdc=PROCESSING_ORDER (enum) :DEFAULT_VALUE (NORMAL)==CURRENT_VALUE (NORMAL)
Arty_Master.xdc=SCOPED_TO_CELLS (string*) :DEFAULT_VALUE ()==CURRENT_VALUE ()
Arty_Master.xdc=SCOPED_TO_REF (string) :DEFAULT_VALUE ()==CURRENT_VALUE ()
Arty_Master.xdc=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation)==CURRENT_VALUE (synthesis implementation)
Arty_Master.xdc=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
Arty_Master.xdc=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
basys.xdc=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (XDC)
basys.xdc=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
basys.xdc=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
basys.xdc=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
basys.xdc=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
basys.xdc=PROCESSING_ORDER (enum) :DEFAULT_VALUE (NORMAL)==CURRENT_VALUE (NORMAL)
basys.xdc=SCOPED_TO_CELLS (string*) :DEFAULT_VALUE ()==CURRENT_VALUE ()
basys.xdc=SCOPED_TO_REF (string) :DEFAULT_VALUE ()==CURRENT_VALUE ()
basys.xdc=USED_IN (string*) :DEFAULT_VALUE (synthesis implementation)==CURRENT_VALUE (synthesis implementation)
basys.xdc=USED_IN_IMPLEMENTATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
basys.xdc=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
CONSTRS_TYPE:(enum) DEFAULT_VALUE (XDC)==CURRENT_VALUE (XDC)
NAME:(string) DEFAULT_VALUE (constrs_1)==CURRENT_VALUE (constrs_1)
TARGET_CONSTRS_FILE:(string) DEFAULT_VALUE ()==CURRENT_VALUE ($PSRCDIR/)
TARGET_PART:(string) DEFAULT_VALUE ()==CURRENT_VALUE (xc7a35tcpg236-1)
vga_driver_test_top_tb.vhd=FILE_TYPE (enum) :DEFAULT_VALUE (Verilog)==CURRENT_VALUE (VHDL)
vga_driver_test_top_tb.vhd=IS_ENABLED (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
vga_driver_test_top_tb.vhd=IS_GLOBAL_INCLUDE (bool) :DEFAULT_VALUE (0)==CURRENT_VALUE (0)
vga_driver_test_top_tb.vhd=LIBRARY (string) :DEFAULT_VALUE (xil_defaultlib)==CURRENT_VALUE (xil_defaultlib)
vga_driver_test_top_tb.vhd=PATH_MODE (enum) :DEFAULT_VALUE (RelativeFirst)==CURRENT_VALUE (RelativeFirst)
vga_driver_test_top_tb.vhd=USED_IN (string*) :DEFAULT_VALUE (synthesis simulation)==CURRENT_VALUE (synthesis simulation)
vga_driver_test_top_tb.vhd=USED_IN_SIMULATION (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
vga_driver_test_top_tb.vhd=USED_IN_SYNTHESIS (bool) :DEFAULT_VALUE (1)==CURRENT_VALUE (1)
32BIT:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
GENERIC:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
HBS.CONFIGURE_DESIGN_FOR_HIER_ACCESS:(bool) DEFAULT_VALUE ()==CURRENT_VALUE (1)
INCLUDE_DIRS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCREMENTAL:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
NAME:(string) DEFAULT_VALUE (sim_1)==CURRENT_VALUE (sim_1)
NL.CELL:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
NL.INCL_UNISIM_MODELS:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
NL.PROCESS_CORNER:(string) DEFAULT_VALUE (slow)==CURRENT_VALUE (slow)
NL.RENAME_TOP:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
NL.SDF_ANNO:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
NL.WRITE_ALL_OVERRIDES:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
SOURCE_SET:(string) DEFAULT_VALUE (sources_1)==CURRENT_VALUE (sources_1)
SYSTEMC_INCLUDE_DIRS:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
TOP:(string) DEFAULT_VALUE ()==CURRENT_VALUE (vga_driver_test_top_tb)
TOP_AUTO_SET:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (0)
TOP_LIB:(string) DEFAULT_VALUE ()==CURRENT_VALUE (xil_defaultlib)
TRANSPORT_INT_DELAY:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
TRANSPORT_PATH_DELAY:(string) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
VERILOG_DEFINE:(string*) DEFAULT_VALUE ()==CURRENT_VALUE ()
VERILOG_UPPERCASE:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XELAB.DLL:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.COMPILE.TCL.PRE:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.COMPILE.XSC.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.COMPILE.XVHDL.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.COMPILE.XVHDL.NOSORT:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.COMPILE.XVHDL.RELAX:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.COMPILE.XVLOG.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.COMPILE.XVLOG.NOSORT:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.COMPILE.XVLOG.RELAX:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.ELABORATE.DEBUG_LEVEL:(enum) DEFAULT_VALUE (typical)==CURRENT_VALUE (typical)
XSIM.ELABORATE.LOAD_GLBL:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.ELABORATE.MT_LEVEL:(enum) DEFAULT_VALUE (auto)==CURRENT_VALUE (auto)
XSIM.ELABORATE.RANGECHECK:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.ELABORATE.RELAX:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
XSIM.ELABORATE.SDF_DELAY:(enum) DEFAULT_VALUE (sdfmax)==CURRENT_VALUE (sdfmax)
XSIM.ELABORATE.SNAPSHOT:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.ELABORATE.XELAB.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.ELABORATE.XSC.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.SIMULATE.ADD_POSITIONAL:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.SIMULATE.CUSTOM_TCL:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.SIMULATE.LOG_ALL_SIGNALS:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.SIMULATE.NO_QUIT:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.SIMULATE.RUNTIME:(string) DEFAULT_VALUE (1000ns)==CURRENT_VALUE (1000ns)
XSIM.SIMULATE.SAIF:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.SIMULATE.SAIF_ALL_SIGNALS:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
XSIM.SIMULATE.SAIF_SCOPE:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.SIMULATE.TCL.POST:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.SIMULATE.WDB:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
XSIM.SIMULATE.XSIM.MORE_OPTIONS:(string) DEFAULT_VALUE ()==CURRENT_VALUE ()
NAME:(string) DEFAULT_VALUE (utils_1)==CURRENT_VALUE (utils_1)
CONSTRSET:(string) DEFAULT_VALUE (constrs_1)==CURRENT_VALUE (constrs_1)
DESCRIPTION:(string) DEFAULT_VALUE (Vivado Synthesis Defaults)==CURRENT_VALUE (Vivado Synthesis Defaults)
FLOW:(string) DEFAULT_VALUE (Vivado Synthesis 2020)==CURRENT_VALUE (Vivado Synthesis 2020)
NAME:(string) DEFAULT_VALUE (synth_1)==CURRENT_VALUE (synth_1)
NEEDS_REFRESH:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
PART:(string) DEFAULT_VALUE ()==CURRENT_VALUE (xc7a35tcpg236-1)
SRCSET:(string) DEFAULT_VALUE (sources_1)==CURRENT_VALUE (sources_1)
INCREMENTAL_CHECKPOINT:(file) DEFAULT_VALUE ()==CURRENT_VALUE ()
AUTO_INCREMENTAL_CHECKPOINT:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
RQS_FILES:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCREMENTAL_CHECKPOINT.MORE_OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCLUDE_IN_ARCHIVE:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
GEN_FULL_BITSTREAM:(unknown) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
WRITE_INCREMENTAL_SYNTH_CHECKPOINT:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STRATEGY:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE (Vivado Synthesis Defaults)
STEPS.SYNTH_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.SYNTH_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY:(unknown) DEFAULT_VALUE (rebuilt)==CURRENT_VALUE (rebuilt)
STEPS.SYNTH_DESIGN.ARGS.GATED_CLOCK_CONVERSION:(unknown) DEFAULT_VALUE (off)==CURRENT_VALUE (off)
STEPS.SYNTH_DESIGN.ARGS.BUFG:(unknown) DEFAULT_VALUE (12)==CURRENT_VALUE (12)
STEPS.SYNTH_DESIGN.ARGS.DIRECTIVE:(unknown) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
STEPS.SYNTH_DESIGN.ARGS.RETIMING:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION:(unknown) DEFAULT_VALUE (auto)==CURRENT_VALUE (auto)
STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.SYNTH_DESIGN.ARGS.RESOURCE_SHARING:(unknown) DEFAULT_VALUE (auto)==CURRENT_VALUE (auto)
STEPS.SYNTH_DESIGN.ARGS.CONTROL_SET_OPT_THRESHOLD:(unknown) DEFAULT_VALUE (auto)==CURRENT_VALUE (auto)
STEPS.SYNTH_DESIGN.ARGS.NO_LC:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.SYNTH_DESIGN.ARGS.NO_SRLEXTRACT:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.SYNTH_DESIGN.ARGS.SHREG_MIN_SIZE:(unknown) DEFAULT_VALUE (3)==CURRENT_VALUE (3)
STEPS.SYNTH_DESIGN.ARGS.MAX_BRAM:(unknown) DEFAULT_VALUE (-1)==CURRENT_VALUE (-1)
STEPS.SYNTH_DESIGN.ARGS.MAX_URAM:(unknown) DEFAULT_VALUE (-1)==CURRENT_VALUE (-1)
STEPS.SYNTH_DESIGN.ARGS.MAX_DSP:(unknown) DEFAULT_VALUE (-1)==CURRENT_VALUE (-1)
STEPS.SYNTH_DESIGN.ARGS.MAX_BRAM_CASCADE_HEIGHT:(unknown) DEFAULT_VALUE (-1)==CURRENT_VALUE (-1)
STEPS.SYNTH_DESIGN.ARGS.MAX_URAM_CASCADE_HEIGHT:(unknown) DEFAULT_VALUE (-1)==CURRENT_VALUE (-1)
STEPS.SYNTH_DESIGN.ARGS.CASCADE_DSP:(unknown) DEFAULT_VALUE (auto)==CURRENT_VALUE (auto)
STEPS.SYNTH_DESIGN.ARGS.ASSERT:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.SYNTH_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
CONSTRSET:(string) DEFAULT_VALUE (constrs_1)==CURRENT_VALUE (constrs_1)
DESCRIPTION:(string) DEFAULT_VALUE (Default settings for Implementation.)==CURRENT_VALUE (Default settings for Implementation.)
FLOW:(string) DEFAULT_VALUE (Vivado Implementation 2020)==CURRENT_VALUE (Vivado Implementation 2020)
NAME:(string) DEFAULT_VALUE (impl_1)==CURRENT_VALUE (impl_1)
NEEDS_REFRESH:(bool) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
PART:(string) DEFAULT_VALUE ()==CURRENT_VALUE (xc7a35tcpg236-1)
PR_CONFIGURATION:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
SRCSET:(string) DEFAULT_VALUE (sources_1)==CURRENT_VALUE (sources_1)
INCREMENTAL_CHECKPOINT:(file) DEFAULT_VALUE ()==CURRENT_VALUE ()
AUTO_INCREMENTAL_CHECKPOINT:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
RQS_FILES:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCREMENTAL_CHECKPOINT.MORE_OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
INCLUDE_IN_ARCHIVE:(bool) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
GEN_FULL_BITSTREAM:(unknown) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STRATEGY:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE (Vivado Implementation Defaults)
STEPS.INIT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.INIT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.OPT_DESIGN.IS_ENABLED:(unknown) DEFAULT_VALUE (1)==CURRENT_VALUE (1)
STEPS.OPT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.OPT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.OPT_DESIGN.ARGS.VERBOSE:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.OPT_DESIGN.ARGS.DIRECTIVE:(unknown) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
STEPS.OPT_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POWER_OPT_DESIGN.IS_ENABLED:(unknown) DEFAULT_VALUE (0)==CURRENT_VALUE (0)
STEPS.POWER_OPT_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POWER_OPT_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.POWER_OPT_DESIGN.ARGS.MORE OPTIONS:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PLACE_DESIGN.TCL.PRE:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PLACE_DESIGN.TCL.POST:(unknown) DEFAULT_VALUE ()==CURRENT_VALUE ()
STEPS.PLACE_DESIGN.ARGS.DIRECTIVE:(unknown) DEFAULT_VALUE (Default)==CURRENT_VALUE (Default)
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